pci: Apply code style changes
- always add {} on any sub-statements
- proper indentation
- 80 chars limit
Change-Id: I869239bf2e309a6e73fb180cf29acf66c019489a
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka
Anas Nashif
parent
15bf447614
commit
1425fd8449
1 changed files with 71 additions and 63 deletions
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@ -14,8 +14,8 @@
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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@ -85,7 +85,7 @@ In order to use the driver, BSP has to define:
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static struct pci_dev_info __noinit dev_info[CONFIG_MAX_PCI_DEVS];
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static int dev_info_index = 0;
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/*******************************************************************************
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/******************************************************************************
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*
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* pci_get_bar_config - return the configuration for the specified BAR
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*
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@ -93,10 +93,10 @@ static int dev_info_index = 0;
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*/
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static int pci_bar_config_get(uint32_t bus,
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uint32_t dev,
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uint32_t func,
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uint32_t bar,
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uint32_t *config)
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uint32_t dev,
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uint32_t func,
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uint32_t bar,
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uint32_t *config)
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{
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union pci_addr_reg pci_ctrl_addr;
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uint32_t old_value;
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@ -109,36 +109,39 @@ static int pci_bar_config_get(uint32_t bus,
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pci_ctrl_addr.field.reg = 4 + bar;
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/* save the current setting */
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(old_value),
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&old_value);
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pci_ctrl_addr,
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sizeof(old_value),
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&old_value);
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/* write to the BAR to see how large it is */
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pci_write(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(uint32_t),
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0xffffffff);
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pci_read(DEFAULT_PCI_CONTROLLER, pci_ctrl_addr, sizeof(*config), config);
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pci_ctrl_addr,
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sizeof(uint32_t),
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0xffffffff);
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(*config),
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config);
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/* put back the old configuration */
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pci_write(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(old_value),
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old_value);
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pci_ctrl_addr,
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sizeof(old_value),
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old_value);
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/* check if this BAR is implemented */
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if (*config != 0xffffffff && *config != 0)
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if (*config != 0xffffffff && *config != 0) {
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return 0;
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}
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/* BAR not supported */
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return -1;
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}
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/*******************************************************************************
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/******************************************************************************
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*
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* pci_bar_params_get - retrieve the I/O address and IRQ of the specified BAR
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*
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@ -150,10 +153,10 @@ static int pci_bar_config_get(uint32_t bus,
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*/
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static inline int pci_bar_params_get(uint32_t bus,
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uint32_t dev,
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uint32_t func,
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uint32_t bar,
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struct pci_dev_info *dev_info)
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uint32_t dev,
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uint32_t func,
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uint32_t bar,
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struct pci_dev_info *dev_info)
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{
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static union pci_addr_reg pci_ctrl_addr;
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uint32_t bar_value;
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@ -169,17 +172,19 @@ static inline int pci_bar_params_get(uint32_t bus,
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pci_ctrl_addr.field.reg = 4 + bar;
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(bar_value),
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&bar_value);
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if (pci_bar_config_get(bus, dev, func, bar, &bar_config) != 0)
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pci_ctrl_addr,
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sizeof(bar_value),
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&bar_value);
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if (pci_bar_config_get(bus, dev, func, bar, &bar_config) != 0) {
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return -1;
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}
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if (BAR_SPACE(bar_config) == BAR_SPACE_MEM) {
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dev_info->mem_type = BAR_SPACE_MEM;
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mask = ~0xf;
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if (bar < 5 && BAR_TYPE(bar_config) == BAR_TYPE_64BIT)
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if (bar < 5 && BAR_TYPE(bar_config) == BAR_TYPE_64BIT) {
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return 1; /* 64-bit MEM */
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}
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} else {
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dev_info->mem_type = BAR_SPACE_IO;
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mask = ~0x3;
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@ -196,7 +201,7 @@ static inline int pci_bar_params_get(uint32_t bus,
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return 0;
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}
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/*******************************************************************************
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/******************************************************************************
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*
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* pci_dev_scan - scan the specified PCI device for all sub functions
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*
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@ -204,10 +209,8 @@ static inline int pci_bar_params_get(uint32_t bus,
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*/
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static void pci_dev_scan(uint32_t bus,
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uint32_t dev,
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uint32_t class_mask /* bitmask, bits set for each needed
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class */
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)
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uint32_t dev,
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uint32_t class_mask)
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{
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uint32_t func;
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uint32_t pci_data;
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@ -222,44 +225,46 @@ static void pci_dev_scan(uint32_t bus,
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}
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/* initialise the PCI controller address register value */
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pci_ctrl_addr.value = 0;
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pci_ctrl_addr.field.enable = 1;
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pci_ctrl_addr.field.bus = bus;
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pci_ctrl_addr.field.device = dev;
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/* scan all the possible functions for this device */
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for (func = 0; func < LSPCI_MAX_FUNC; func++) {
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pci_ctrl_addr.field.func = func;
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(pci_data),
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&pci_data);
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if (pci_data == 0xffffffff)
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(pci_data),
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&pci_data);
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if (pci_data == 0xffffffff) {
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continue;
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}
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/* get the PCI header from the device */
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pci_header_get(
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DEFAULT_PCI_CONTROLLER, bus, dev, func, &pci_dev_header);
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pci_header_get(DEFAULT_PCI_CONTROLLER,
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bus, dev, func, &pci_dev_header);
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/* Skip a device if it's class is not specified by the caller */
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if (!((1 << pci_dev_header.field.class) & class_mask))
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if (!((1 << pci_dev_header.field.class) & class_mask)) {
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continue;
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}
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/* Get memory and interrupt information */
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if ((pci_dev_header.field.hdr_type & 0x7f) == 1)
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if ((pci_dev_header.field.hdr_type & 0x7f) == 1) {
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max_bars = 2;
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else
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} else {
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max_bars = MAX_BARS;
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}
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for (i = 0; i < max_bars; ++i) {
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/* Ignore BARs with errors and 64 bit BARs */
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if (pci_bar_params_get(
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bus, dev, func, i, dev_info + dev_info_index) !=
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0)
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if (pci_bar_params_get(bus, dev, func, i,
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dev_info + dev_info_index) != 0) {
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continue;
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else {
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} else {
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dev_info[dev_info_index].vendor_id =
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pci_dev_header.field.vendor_id;
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dev_info[dev_info_index].device_id =
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@ -278,7 +283,7 @@ static void pci_dev_scan(uint32_t bus,
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}
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}
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/*******************************************************************************
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/******************************************************************************
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*
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* pci_bus_scan - scans PCI bus for devices
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*
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@ -290,8 +295,7 @@ static void pci_dev_scan(uint32_t bus,
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* \NOMANUAL
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*/
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void pci_bus_scan(uint32_t class_mask /* bitmask, bits set for each needed class */
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)
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void pci_bus_scan(uint32_t class_mask)
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{
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uint32_t bus;
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uint32_t dev;
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@ -305,24 +309,26 @@ void pci_bus_scan(uint32_t class_mask /* bitmask, bits set for each needed class
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/* run through the buses and devices */
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for (bus = 0; bus < LSPCI_MAX_BUS; bus++) {
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for (dev = 0; (dev < LSPCI_MAX_DEV) &&
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(dev_info_index < CONFIG_MAX_PCI_DEVS);
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(dev_info_index < CONFIG_MAX_PCI_DEVS);
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dev++) {
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pci_ctrl_addr.field.bus = bus;
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pci_ctrl_addr.field.device = dev;
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/* try and read register zero of the first function */
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(pci_data),
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&pci_data);
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pci_ctrl_addr,
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sizeof(pci_data),
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&pci_data);
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/* scan the device if we found something */
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if (pci_data != 0xffffffff)
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if (pci_data != 0xffffffff) {
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pci_dev_scan(bus, dev, class_mask);
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}
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}
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}
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}
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/*******************************************************************************
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/******************************************************************************
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*
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* pci_info_get - returns list of PCI devices
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*
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@ -333,7 +339,7 @@ struct pci_dev_info *pci_info_get(void)
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return dev_info;
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}
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/*******************************************************************************
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/******************************************************************************
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*
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* pci_dev_find - find PCI device of a specified class and specified index
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*
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@ -355,8 +361,9 @@ int pci_dev_find(int class, int idx, uint32_t *addr, uint32_t *size, int *irq)
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int j;
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for (i = 0, j = 0; i < dev_info_index; i++) {
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if (dev_info[i].class != class)
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if (dev_info[i].class != class) {
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continue;
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}
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if (j == idx) {
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*addr = dev_info[i].addr;
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@ -366,11 +373,12 @@ int pci_dev_find(int class, int idx, uint32_t *addr, uint32_t *size, int *irq)
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}
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j++;
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}
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return -1;
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}
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#ifdef PCI_DEBUG
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/*******************************************************************************
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/******************************************************************************
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*
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* pci_show - Show PCI devices
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*
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