From d280d89214ac442e093532c64fbf0cfc9199ab92 Mon Sep 17 00:00:00 2001 From: Harris Tomy Date: Wed, 4 Jun 2025 08:08:20 +0000 Subject: [PATCH] dts/kconfig: stm32u5: add f9 and clean up dts node locations Adds skeleton dtsi for u5f9 for u5g9 to inherit from Moves the peripheral nodes into dtsi's that actually has the peripheral and includes them for SoC's higher in the series where applicable. signed-off-by: Harris Tomy --- boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts | 1 + dts/arm/st/u5/stm32u5.dtsi | 81 +------------------ dts/arm/st/u5/stm32u535.dtsi | 37 +++------ dts/arm/st/u5/stm32u535Xb.dtsi | 10 --- dts/arm/st/u5/stm32u535Xc.dtsi | 10 --- dts/arm/st/u5/stm32u535Xe.dtsi | 10 --- dts/arm/st/u5/stm32u545.dtsi | 26 +----- dts/arm/st/u5/stm32u545Xe.dtsi | 10 --- dts/arm/st/u5/stm32u575.dtsi | 34 +++----- dts/arm/st/u5/stm32u575Xg.dtsi | 10 --- dts/arm/st/u5/stm32u575Xi.dtsi | 6 +- dts/arm/st/u5/stm32u585.dtsi | 2 + dts/arm/st/u5/stm32u585Xi.dtsi | 6 +- dts/arm/st/u5/stm32u595.dtsi | 34 +++----- dts/arm/st/u5/stm32u599.dtsi | 11 +++ dts/arm/st/u5/stm32u599Xi.dtsi | 9 --- dts/arm/st/u5/stm32u599Xj.dtsi | 10 +-- dts/arm/st/u5/stm32u5_crypt.dtsi | 18 +++++ dts/arm/st/u5/stm32u5_extra.dtsi | 79 ++++++++++++++++++ dts/arm/st/u5/stm32u5_usb_fs.dtsi | 30 +++++++ dts/arm/st/u5/stm32u5_usbotg_fs.dtsi | 31 +++++++ dts/arm/st/u5/stm32u5_usbotg_hs.dtsi | 32 ++++++++ dts/arm/st/u5/stm32u5a5.dtsi | 2 + dts/arm/st/u5/stm32u5a5Xj.dtsi | 10 +-- dts/arm/st/u5/stm32u5a9.dtsi | 4 +- dts/arm/st/u5/stm32u5a9Xj.dtsi | 11 +-- dts/arm/st/u5/stm32u5f9.dtsi | 19 +++++ dts/arm/st/u5/stm32u5g9.dtsi | 17 +--- dts/arm/st/u5/stm32u5g9Xj.dtsi | 12 +-- .../stm32u5x/Kconfig.defconfig.stm32u5f9xx | 11 +++ soc/st/stm32/stm32u5x/Kconfig.soc | 5 ++ 31 files changed, 292 insertions(+), 296 deletions(-) create mode 100644 dts/arm/st/u5/stm32u5_crypt.dtsi create mode 100644 dts/arm/st/u5/stm32u5_extra.dtsi create mode 100644 dts/arm/st/u5/stm32u5_usb_fs.dtsi create mode 100644 dts/arm/st/u5/stm32u5_usbotg_fs.dtsi create mode 100644 dts/arm/st/u5/stm32u5_usbotg_hs.dtsi create mode 100644 dts/arm/st/u5/stm32u5f9.dtsi create mode 100644 soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5f9xx diff --git a/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts b/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts index a2425e4cc3d..368dd1d04f7 100644 --- a/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts +++ b/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include +#include #include / { diff --git a/dts/arm/st/u5/stm32u5.dtsi b/dts/arm/st/u5/stm32u5.dtsi index 304a578a1ff..55cb38d2581 100644 --- a/dts/arm/st/u5/stm32u5.dtsi +++ b/dts/arm/st/u5/stm32u5.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021 Linaro Limited * Copyright (c) 2023 PSICONTROL nv * Copyright (c) 2024 STMicroelectronics + * Copyright (c) 2025 Harris Tomy * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -253,14 +253,6 @@ clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; }; - gpiof: gpio@42021400 { - compatible = "st,stm32-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x42021400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 5U)>; - }; - gpiog: gpio@42021800 { compatible = "st,stm32-gpio"; gpio-controller; @@ -276,14 +268,6 @@ reg = <0x42021c00 0x400>; clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; }; - - gpioi: gpio@42022000 { - compatible = "st,stm32-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x42022000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 8U)>; - }; }; iwdg: watchdog@40003000 { @@ -318,15 +302,6 @@ status = "disabled"; }; - usart2: serial@40004400 { - compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; - resets = <&rctl STM32_RESET(APB1L, 17U)>; - interrupts = <62 0>; - status = "disabled"; - }; - usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; @@ -731,28 +706,6 @@ status = "disabled"; }; - octospi2: spi@420d2400 { - compatible = "st,stm32-ospi"; - reg = <0x420d2400 0x400>; - interrupts = <120 0>; - clock-names = "ospix", "ospi-ker", "ospi-mgr"; - clocks = <&rcc STM32_CLOCK(AHB2_2, 8U)>, - <&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>, - <&rcc STM32_CLOCK(AHB2, 21U)>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - - aes: aes@420c0000 { - compatible = "st,stm32-aes"; - reg = <0x420c0000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; - resets = <&rctl STM32_RESET(AHB2L, 16U)>; - interrupts = <93 0>; - status = "disabled"; - }; - rng: rng@420c0800 { compatible = "st,stm32-rng"; reg = <0x420c0800 0x400>; @@ -782,16 +735,6 @@ status = "disabled"; }; - sdmmc2: sdmmc@420c8c00 { - compatible = "st,stm32-sdmmc"; - reg = <0x420c8c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 28U)>, - <&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>; - resets = <&rctl STM32_RESET(AHB2L, 28U)>; - interrupts = <79 0>; - status = "disabled"; - }; - dac1: dac@46021800 { compatible = "st,stm32-dac"; reg = <0x46021800 0x400>; @@ -848,14 +791,6 @@ status = "disabled"; }; - ucpd1: ucpd@4000dc00 { - compatible = "st,stm32-ucpd"; - reg = <0x4000dc00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; - interrupts = <106 0>; - status = "disabled"; - }; - gpdma1: dma@40020000 { compatible = "st,stm32u5-dma"; #dma-cells = <3>; @@ -869,20 +804,6 @@ status = "disabled"; }; - fmc: memory-controller@420d0400 { - compatible = "st,stm32-fmc"; - reg = <0x420d0400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2_2, 0U)>; - status = "disabled"; - - sram { - compatible = "st,stm32-fmc-nor-psram"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - pwr: power@46020800 { compatible = "st,stm32-pwr"; reg = <0x46020800 0x400>; /* PWR register bank */ diff --git a/dts/arm/st/u5/stm32u535.dtsi b/dts/arm/st/u5/stm32u535.dtsi index 5e794fed61b..b2ae9ebbf43 100644 --- a/dts/arm/st/u5/stm32u535.dtsi +++ b/dts/arm/st/u5/stm32u535.dtsi @@ -4,35 +4,20 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include / { - soc { - /* USB-C PD is not available on this part. */ - /delete-node/ ucpd@4000dc00; - - /* Advanced Encryption Standard HW accelerator is not available on this part. */ - /delete-node/ aes@420c0000; - - compatible = "st,stm32u535", "st,stm32u5", "simple-bus"; - - usb: usb@40016000 { - compatible = "st,stm32-usb"; - reg = <0x40016000 0x400>; - interrupts = <73 0>; - interrupt-names = "usb"; - num-bidir-endpoints = <8>; - ram-size = <2048>; - maximum-speed = "full-speed"; - clocks = <&rcc STM32_CLOCK(APB2, 24)>, - <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>; - phys = <&usb_fs_phy>; - status = "disabled"; - }; + sram0: memory@20000000 { + /* SRAM1 + SRAM2 */ + reg = <0x20000000 DT_SIZE_K(256)>; }; - usb_fs_phy: usb_fs_phy { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; + sram1: memory@28000000 { + /* SRAM4, low-power background autonomous mode */ + reg = <0x28000000 DT_SIZE_K(16)>; + }; + + soc { + compatible = "st,stm32u535", "st,stm32u5", "simple-bus"; }; }; diff --git a/dts/arm/st/u5/stm32u535Xb.dtsi b/dts/arm/st/u5/stm32u535Xb.dtsi index f937454d89e..b4d0ab07059 100644 --- a/dts/arm/st/u5/stm32u535Xb.dtsi +++ b/dts/arm/st/u5/stm32u535Xb.dtsi @@ -8,16 +8,6 @@ #include / { - sram0: memory@20000000 { - /* SRAM1 + SRAM2 */ - reg = <0x20000000 DT_SIZE_K(256)>; - }; - - sram1: memory@28000000 { - /* SRAM4, low-power background autonomous mode */ - reg = <0x28000000 DT_SIZE_K(16)>; - }; - soc { flash-controller@40022000 { flash0: flash@8000000 { diff --git a/dts/arm/st/u5/stm32u535Xc.dtsi b/dts/arm/st/u5/stm32u535Xc.dtsi index d1bc5e4cb81..79fc4d62594 100644 --- a/dts/arm/st/u5/stm32u535Xc.dtsi +++ b/dts/arm/st/u5/stm32u535Xc.dtsi @@ -8,16 +8,6 @@ #include / { - sram0: memory@20000000 { - /* SRAM1 + SRAM2 */ - reg = <0x20000000 DT_SIZE_K(256)>; - }; - - sram1: memory@28000000 { - /* SRAM4, low-power background autonomous mode */ - reg = <0x28000000 DT_SIZE_K(16)>; - }; - soc { flash-controller@40022000 { flash0: flash@8000000 { diff --git a/dts/arm/st/u5/stm32u535Xe.dtsi b/dts/arm/st/u5/stm32u535Xe.dtsi index fc38b322864..3586d633dba 100644 --- a/dts/arm/st/u5/stm32u535Xe.dtsi +++ b/dts/arm/st/u5/stm32u535Xe.dtsi @@ -8,16 +8,6 @@ #include / { - sram0: memory@20000000 { - /* SRAM1 + SRAM2 */ - reg = <0x20000000 DT_SIZE_K(256)>; - }; - - sram1: memory@28000000 { - /* SRAM4, low-power background autonomous mode */ - reg = <0x28000000 DT_SIZE_K(16)>; - }; - soc { flash-controller@40022000 { flash0: flash@8000000 { diff --git a/dts/arm/st/u5/stm32u545.dtsi b/dts/arm/st/u5/stm32u545.dtsi index c034e6a2727..f8ef20e3c84 100644 --- a/dts/arm/st/u5/stm32u545.dtsi +++ b/dts/arm/st/u5/stm32u545.dtsi @@ -4,33 +4,11 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include - +#include +#include / { soc { - /* USB-C PD is not available on this part. */ - /delete-node/ ucpd@4000dc00; - compatible = "st,stm32u545", "st,stm32u5", "simple-bus"; - - usb: usb@40006000 { - compatible = "st,stm32-usb"; - reg = <0x40006000 0x400>; - interrupts = <73 0>; - interrupt-names = "usb"; - num-bidir-endpoints = <8>; - ram-size = <1024>; - maximum-speed = "full-speed"; - status = "disabled"; - clocks = <&rcc STM32_CLOCK(APB2, 24U)>, - <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>; - phys = <&usb_fs_phy>; - }; - }; - - usb_fs_phy: usb_fs_phy { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; }; }; diff --git a/dts/arm/st/u5/stm32u545Xe.dtsi b/dts/arm/st/u5/stm32u545Xe.dtsi index 52f2bf0c4c5..e3af68d2ddb 100644 --- a/dts/arm/st/u5/stm32u545Xe.dtsi +++ b/dts/arm/st/u5/stm32u545Xe.dtsi @@ -7,16 +7,6 @@ #include / { - sram0: memory@20000000 { - /* SRAM1 + SRAM2 */ - reg = <0x20000000 DT_SIZE_K(256)>; - }; - - sram1: memory@28000000 { - /* SRAM4, low-power background autonomous mode */ - reg = <0x28000000 DT_SIZE_K(16)>; - }; - soc { flash-controller@40022000 { flash0: flash@8000000 { diff --git a/dts/arm/st/u5/stm32u575.dtsi b/dts/arm/st/u5/stm32u575.dtsi index eafda700e85..1db3c8325e1 100644 --- a/dts/arm/st/u5/stm32u575.dtsi +++ b/dts/arm/st/u5/stm32u575.dtsi @@ -1,33 +1,25 @@ /* * Copyright (c) 2021 Linaro Limited + * Copyright (c) 2025 Harris Tomy * * SPDX-License-Identifier: Apache-2.0 */ -#include - +#include +#include / { + sram0: memory@20000000 { + /* SRAM1 + SRAM2 + SRAM3 */ + reg = <0x20000000 DT_SIZE_K(768)>; + }; + + sram1: memory@28000000 { + /* SRAM4, low-power background autonomous mode */ + reg = <0x28000000 DT_SIZE_K(16)>; + }; + soc { compatible = "st,stm32u575", "st,stm32u5", "simple-bus"; - - usbotg_fs: otgfs@42040000 { - compatible = "st,stm32-otgfs"; - reg = <0x42040000 0x80000>; - interrupts = <73 0>; - interrupt-names = "otgfs"; - num-bidir-endpoints = <6>; - ram-size = <1280>; - maximum-speed = "full-speed"; - clocks = <&rcc STM32_CLOCK(AHB2, 14U)>, - <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>; - phys = <&otgfs_phy>; - status = "disabled"; - }; - }; - - otgfs_phy: otgfs_phy { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; }; }; diff --git a/dts/arm/st/u5/stm32u575Xg.dtsi b/dts/arm/st/u5/stm32u575Xg.dtsi index 7d92f1613e8..110897534d2 100644 --- a/dts/arm/st/u5/stm32u575Xg.dtsi +++ b/dts/arm/st/u5/stm32u575Xg.dtsi @@ -7,16 +7,6 @@ #include / { - sram0: memory@20000000 { - /* SRAM1 + SRAM2 + SRAM3 */ - reg = <0x20000000 DT_SIZE_K(768)>; - }; - - sram1: memory@28000000 { - /* SRAM4, low-power background autonomous mode */ - reg = <0x28000000 DT_SIZE_K(16)>; - }; - soc { flash-controller@40022000 { flash0: flash@8000000 { diff --git a/dts/arm/st/u5/stm32u575Xi.dtsi b/dts/arm/st/u5/stm32u575Xi.dtsi index 3d83661c9a5..77223f3e954 100644 --- a/dts/arm/st/u5/stm32u575Xi.dtsi +++ b/dts/arm/st/u5/stm32u575Xi.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2021 Linaro Limited + * Copyright (c) 2025 Harris Tomy * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,11 +8,6 @@ #include / { - sram0: memory@20000000 { - /* SRAM1 + SRAM2 + SRAM3 */ - reg = <0x20000000 DT_SIZE_K(768)>; - }; - soc { flash-controller@40022000 { flash0: flash@8000000 { diff --git a/dts/arm/st/u5/stm32u585.dtsi b/dts/arm/st/u5/stm32u585.dtsi index aa424a5d34e..e12a7f0d679 100644 --- a/dts/arm/st/u5/stm32u585.dtsi +++ b/dts/arm/st/u5/stm32u585.dtsi @@ -1,10 +1,12 @@ /* * Copyright (c) 2021 Linaro Limited + * Copyright (c) 2025 Harris Tomy * * SPDX-License-Identifier: Apache-2.0 */ #include +#include / { soc { diff --git a/dts/arm/st/u5/stm32u585Xi.dtsi b/dts/arm/st/u5/stm32u585Xi.dtsi index caef7d19824..fc2dedbf86f 100644 --- a/dts/arm/st/u5/stm32u585Xi.dtsi +++ b/dts/arm/st/u5/stm32u585Xi.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2021 Linaro Limited + * Copyright (c) 2025 Harris Tomy * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,11 +8,6 @@ #include / { - sram0: memory@20000000 { - /* SRAM1 + SRAM2 + SRAM3 */ - reg = <0x20000000 DT_SIZE_K(768)>; - }; - soc { flash-controller@40022000 { flash0: flash@8000000 { diff --git a/dts/arm/st/u5/stm32u595.dtsi b/dts/arm/st/u5/stm32u595.dtsi index f3fc9985967..2193f839ae3 100644 --- a/dts/arm/st/u5/stm32u595.dtsi +++ b/dts/arm/st/u5/stm32u595.dtsi @@ -1,14 +1,24 @@ /* * Copyright (c) 2023 PSICONTROl nv * Copyright (c) 2023 STMicroelectronics + * Copyright (c) 2025 Harris Tomy * * SPDX-License-Identifier: Apache-2.0 */ -#include - +#include / { + sram0: memory@20000000 { + /* SRAM1 + SRAM2 + SRAM3 + SRAM5 */ + reg = <0x20000000 DT_SIZE_K(2496)>; + }; + + sram1: memory@28000000 { + /* SRAM4 */ + reg = <0x28000000 DT_SIZE_K(16)>; + }; + soc { compatible = "st,stm32u595", "st,stm32u5", "simple-bus"; @@ -99,26 +109,6 @@ st,adc-sequencer = "FULLY_CONFIGURABLE"; st,adc-oversampler = "OVERSAMPLER_EXTENDED"; }; - - usbotg_hs: otghs@42040000 { - compatible = "st,stm32-otghs"; - reg = <0x42040000 0x20000>; - interrupts = <73 0>; - interrupt-names = "otghs"; - num-bidir-endpoints = <9>; - ram-size = <4096>; - maximum-speed = "high-speed"; - clocks = <&rcc STM32_CLOCK(AHB2, 14)>; - phys = <&otghs_phy>; - status = "disabled"; - }; - }; - - otghs_phy: otghs_phy { - compatible = "st,stm32u5-otghs-phy"; - clocks = <&rcc STM32_CLOCK(AHB2, 15U)>, - <&rcc STM32_SRC_HSE OTGHS_SEL(0)>; - #phy-cells = <0>; }; smbus5: smbus5 { diff --git a/dts/arm/st/u5/stm32u599.dtsi b/dts/arm/st/u5/stm32u599.dtsi index f72d22c5f1a..7a186ef9cd6 100644 --- a/dts/arm/st/u5/stm32u599.dtsi +++ b/dts/arm/st/u5/stm32u599.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2023 PSICONTROL nv + * Copyright (c) 2025 Harris Tomy * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,5 +10,15 @@ / { soc { compatible = "st,stm32u599", "st,stm32u5", "simple-bus"; + + ltdc: display-controller@40016800 { + compatible = "st,stm32-ltdc"; + reg = <0x40016800 0x400>; + interrupts = <135 0>, <136 0>; + interrupt-names = "ltdc", "ltdc_er"; + clocks = <&rcc STM32_CLOCK(APB2, 26)>; + resets = <&rctl STM32_RESET(APB2, 26)>; + status = "disabled"; + }; }; }; diff --git a/dts/arm/st/u5/stm32u599Xi.dtsi b/dts/arm/st/u5/stm32u599Xi.dtsi index 3a4bb02f0e6..be05acee344 100644 --- a/dts/arm/st/u5/stm32u599Xi.dtsi +++ b/dts/arm/st/u5/stm32u599Xi.dtsi @@ -7,15 +7,6 @@ #include / { - sram0: memory@20000000 { - /* SRAM1 + SRAM2 + SRAM3 + SRAM5 */ - reg = <0x20000000 DT_SIZE_K(2496)>; - }; - sram1: memory@28000000 { - /* SRAM4 */ - reg = <0x28000000 DT_SIZE_K(16)>; - }; - soc { flash-controller@40022000 { flash0: flash@8000000 { diff --git a/dts/arm/st/u5/stm32u599Xj.dtsi b/dts/arm/st/u5/stm32u599Xj.dtsi index f0eb2568ea6..fb2c69c4397 100644 --- a/dts/arm/st/u5/stm32u599Xj.dtsi +++ b/dts/arm/st/u5/stm32u599Xj.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2023 PSICONTROL nv + * Copyright (c) 2025 Harris Tomy * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,15 +8,6 @@ #include / { - sram0: memory@20000000 { - /* SRAM1 + SRAM2 + SRAM3 + SRAM5 */ - reg = <0x20000000 DT_SIZE_K(2496)>; - }; - sram1: memory@28000000 { - /* SRAM4 */ - reg = <0x28000000 DT_SIZE_K(16)>; - }; - soc { flash-controller@40022000 { flash0: flash@8000000 { diff --git a/dts/arm/st/u5/stm32u5_crypt.dtsi b/dts/arm/st/u5/stm32u5_crypt.dtsi new file mode 100644 index 00000000000..6b36a01f9f1 --- /dev/null +++ b/dts/arm/st/u5/stm32u5_crypt.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2025 Harris Tomy + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + soc { + aes: aes@420c0000 { + compatible = "st,stm32-aes"; + reg = <0x420c0000 0x400>; + clocks = <&rcc STM32_CLOCK(AHB2, 16)>; + resets = <&rctl STM32_RESET(AHB2L, 16)>; + interrupts = <93 0>; + status = "disabled"; + }; + }; +}; diff --git a/dts/arm/st/u5/stm32u5_extra.dtsi b/dts/arm/st/u5/stm32u5_extra.dtsi new file mode 100644 index 00000000000..9f329ea9ef0 --- /dev/null +++ b/dts/arm/st/u5/stm32u5_extra.dtsi @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2025 Harris Tomy + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + soc { + usart2: serial@40004400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004400 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; + resets = <&rctl STM32_RESET(APB1L, 17)>; + interrupts = <62 0>; + status = "disabled"; + }; + + gpiof: gpio@42021400 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42021400 0x400>; + clocks = <&rcc STM32_CLOCK(AHB2, 5)>; + }; + + gpioi: gpio@42022000 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42022000 0x400>; + clocks = <&rcc STM32_CLOCK(AHB2, 8)>; + }; + + sdmmc2: sdmmc@420c8c00 { + compatible = "st,stm32-sdmmc"; + reg = <0x420c8c00 0x400>; + clocks = <&rcc STM32_CLOCK(AHB2, 28)>, + <&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>; + resets = <&rctl STM32_RESET(AHB2L, 28)>; + interrupts = <79 0>; + status = "disabled"; + }; + + fmc: memory-controller@420d0400 { + compatible = "st,stm32-fmc"; + reg = <0x420d0400 0x400>; + clocks = <&rcc STM32_CLOCK(AHB2_2, 0)>; + status = "disabled"; + + sram { + compatible = "st,stm32-fmc-nor-psram"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + octospi2: spi@420d2400 { + compatible = "st,stm32-ospi"; + reg = <0x420d2400 0x400>; + interrupts = <120 0>; + clock-names = "ospix", "ospi-ker", "ospi-mgr"; + clocks = <&rcc STM32_CLOCK(AHB2_2, 8)>, + <&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>, + <&rcc STM32_CLOCK(AHB2, 21)>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + ucpd1: ucpd@4000dc00 { + compatible = "st,stm32-ucpd"; + reg = <0x4000dc00 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; + interrupts = <106 0>; + status = "disabled"; + }; + }; +}; diff --git a/dts/arm/st/u5/stm32u5_usb_fs.dtsi b/dts/arm/st/u5/stm32u5_usb_fs.dtsi new file mode 100644 index 00000000000..eee88fdd2d1 --- /dev/null +++ b/dts/arm/st/u5/stm32u5_usb_fs.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025 Harris Tomy + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + usb: usb@40016000 { + compatible = "st,stm32-usb"; + reg = <0x40016000 0x400>; + interrupts = <73 0>; + interrupt-names = "usb"; + num-bidir-endpoints = <8>; + ram-size = <2048>; + maximum-speed = "full-speed"; + clocks = <&rcc STM32_CLOCK(APB2, 24)>, + <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>; + phys = <&usb_fs_phy>; + status = "disabled"; + }; + }; + + usb_fs_phy: usb_fs_phy { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; diff --git a/dts/arm/st/u5/stm32u5_usbotg_fs.dtsi b/dts/arm/st/u5/stm32u5_usbotg_fs.dtsi new file mode 100644 index 00000000000..2e9f2bc6df0 --- /dev/null +++ b/dts/arm/st/u5/stm32u5_usbotg_fs.dtsi @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2025 Harris Tomy + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + usbotg_fs: otgfs@42040000 { + compatible = "st,stm32-otgfs"; + reg = <0x42040000 0x80000>; + interrupts = <73 0>; + interrupt-names = "otgfs"; + num-bidir-endpoints = <6>; + ram-size = <1280>; + maximum-speed = "full-speed"; + clocks = <&rcc STM32_CLOCK(AHB2, 14)>, + <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>; + phys = <&otgfs_phy>; + status = "disabled"; + }; + }; + + otgfs_phy: otgfs_phy { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; diff --git a/dts/arm/st/u5/stm32u5_usbotg_hs.dtsi b/dts/arm/st/u5/stm32u5_usbotg_hs.dtsi new file mode 100644 index 00000000000..c9de83ea72d --- /dev/null +++ b/dts/arm/st/u5/stm32u5_usbotg_hs.dtsi @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2025 Harris Tomy + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + usbotg_hs: otghs@42040000 { + compatible = "st,stm32-otghs"; + reg = <0x42040000 0x20000>; + interrupts = <73 0>; + interrupt-names = "otghs"; + num-bidir-endpoints = <9>; + ram-size = <4096>; + maximum-speed = "high-speed"; + clocks = <&rcc STM32_CLOCK(AHB2, 14)>; + phys = <&otghs_phy>; + status = "disabled"; + }; + }; + + otghs_phy: otghs_phy { + compatible = "st,stm32u5-otghs-phy"; + clocks = <&rcc STM32_CLOCK(AHB2, 15)>, + <&rcc STM32_SRC_HSE OTGHS_SEL(0)>; + #phy-cells = <0>; + }; +}; diff --git a/dts/arm/st/u5/stm32u5a5.dtsi b/dts/arm/st/u5/stm32u5a5.dtsi index bc8ba619020..99ab50212ca 100644 --- a/dts/arm/st/u5/stm32u5a5.dtsi +++ b/dts/arm/st/u5/stm32u5a5.dtsi @@ -1,10 +1,12 @@ /* * Copyright (c) 2023 STMicroelectronics + * Copyright (c) 2025 Harris Tomy * * SPDX-License-Identifier: Apache-2.0 */ #include +#include / { soc { diff --git a/dts/arm/st/u5/stm32u5a5Xj.dtsi b/dts/arm/st/u5/stm32u5a5Xj.dtsi index 6719e89619d..2a1e265c6f7 100644 --- a/dts/arm/st/u5/stm32u5a5Xj.dtsi +++ b/dts/arm/st/u5/stm32u5a5Xj.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2023 STMicroelectronics + * Copyright (c) 2025 Harris Tomy * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,15 +9,6 @@ #include / { - sram0: memory@20000000 { - /* SRAM1 + SRAM2 + SRAM3 + SRAM5 */ - reg = <0x20000000 DT_SIZE_K(2496)>; - }; - sram1: memory@28000000 { - /* SRAM4 */ - reg = <0x28000000 DT_SIZE_K(16)>; - }; - soc { flash-controller@40022000 { flash0: flash@8000000 { diff --git a/dts/arm/st/u5/stm32u5a9.dtsi b/dts/arm/st/u5/stm32u5a9.dtsi index 13cd1e1401d..8fe338854d4 100644 --- a/dts/arm/st/u5/stm32u5a9.dtsi +++ b/dts/arm/st/u5/stm32u5a9.dtsi @@ -1,10 +1,12 @@ /* * Copyright (c) 2023 STMicroelectronics + * Copyright (c) 2025 Harris Tomy * * SPDX-License-Identifier: Apache-2.0 */ -#include +#include +#include / { soc { diff --git a/dts/arm/st/u5/stm32u5a9Xj.dtsi b/dts/arm/st/u5/stm32u5a9Xj.dtsi index 1b9b7cadd75..7d89265da77 100644 --- a/dts/arm/st/u5/stm32u5a9Xj.dtsi +++ b/dts/arm/st/u5/stm32u5a9Xj.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2023 STMicroelectronics + * Copyright (c) 2025 Harris Tomy * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,16 +9,6 @@ #include / { - sram0: memory@20000000 { - /* SRAM1 + SRAM2 + SRAM3 + SRAM5 */ - /* 768K + 64K + 832K + 832K */ - reg = <0x20000000 DT_SIZE_K(2496)>; - }; - sram1: memory@28000000 { - /* SRAM4, low-power background autonomous mode */ - reg = <0x28000000 DT_SIZE_K(16)>; - }; - soc { flash-controller@40022000 { flash0: flash@8000000 { diff --git a/dts/arm/st/u5/stm32u5f9.dtsi b/dts/arm/st/u5/stm32u5f9.dtsi new file mode 100644 index 00000000000..786fd9a9d4a --- /dev/null +++ b/dts/arm/st/u5/stm32u5f9.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Harris Tomy + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + compatible = "st,stm32u5f9", "st,stm32u5", "simple-bus"; + }; +}; + +&sram0 { + /* SRAM1 + SRAM2 + SRAM3 + SRAM5 + SRAM6 */ + /* 768K + 64K + 832K + 832K + 512K */ + reg = <0x20000000 DT_SIZE_K(3008)>; +}; diff --git a/dts/arm/st/u5/stm32u5g9.dtsi b/dts/arm/st/u5/stm32u5g9.dtsi index fe4fe181232..1e0495a1df9 100644 --- a/dts/arm/st/u5/stm32u5g9.dtsi +++ b/dts/arm/st/u5/stm32u5g9.dtsi @@ -1,26 +1,15 @@ /* * Copyright (c) 2025 Charles Dias + * Copyright (c) 2025 Harris Tomy * * SPDX-License-Identifier: Apache-2.0 */ -#include -#include -#include -#include +#include +#include / { soc { compatible = "st,stm32u5g9", "st,stm32u5", "simple-bus"; - - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x400>; - interrupts = <135 0>, <136 0>; - interrupt-names = "ltdc", "ltdc_er"; - clocks = <&rcc STM32_CLOCK(APB2, 26)>; - resets = <&rctl STM32_RESET(APB2, 26)>; - status = "disabled"; - }; }; }; diff --git a/dts/arm/st/u5/stm32u5g9Xj.dtsi b/dts/arm/st/u5/stm32u5g9Xj.dtsi index 6116c30fc2a..f1df71d48ee 100644 --- a/dts/arm/st/u5/stm32u5g9Xj.dtsi +++ b/dts/arm/st/u5/stm32u5g9Xj.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2025 Charles Dias + * Copyright (c) 2025 Harris Tomy * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,17 +9,6 @@ #include / { - sram0: memory@20000000 { - /* SRAM1 + SRAM2 + SRAM3 + SRAM5 + SRAM6 */ - /* 768K + 64K + 832K + 832K + 512K */ - reg = <0x20000000 DT_SIZE_K(3008)>; - }; - - sram4: memory@28000000 { - /* SRAM4, low-power background autonomous mode */ - reg = <0x28000000 DT_SIZE_K(16)>; - }; - soc { flash-controller@40022000 { flash0: flash@8000000 { diff --git a/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5f9xx b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5f9xx new file mode 100644 index 00000000000..df0a6cd4398 --- /dev/null +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5f9xx @@ -0,0 +1,11 @@ +# STMicroelectronics STM32U5GFXX MCU + +# Copyright (c) 2025 Harris Tomy +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32U5F9XX + +config NUM_IRQS + default 141 + +endif # SOC_STM32U5F9XX diff --git a/soc/st/stm32/stm32u5x/Kconfig.soc b/soc/st/stm32/stm32u5x/Kconfig.soc index e6c26498744..7b6f6c0f844 100644 --- a/soc/st/stm32/stm32u5x/Kconfig.soc +++ b/soc/st/stm32/stm32u5x/Kconfig.soc @@ -46,6 +46,10 @@ config SOC_STM32U5A9XX bool select SOC_SERIES_STM32U5X +config SOC_STM32U5F9XX + bool + select SOC_SERIES_STM32U5X + config SOC_STM32U5G9XX bool select SOC_SERIES_STM32U5X @@ -53,6 +57,7 @@ config SOC_STM32U5G9XX config SOC default "stm32u5a5xx" if SOC_STM32U5A5XX default "stm32u5a9xx" if SOC_STM32U5A9XX + default "stm32u5f9xx" if SOC_STM32U5F9XX default "stm32u5g9xx" if SOC_STM32U5G9XX default "stm32u535xx" if SOC_STM32U535XX default "stm32u545xx" if SOC_STM32U545XX