board: x86: add new board qemu_x86_lakemont

This adds a new board qemu_x86_lakemont for testing
the Lakemont SoC configuration.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>

boards/x86/qemu_x86/Kconfig.board

@@ -13,3 +13,10 @@ config BOARD_QEMU_X86_64
 	select QEMU_TARGET
 	select X86_64
 	select HAS_COVERAGE_SUPPORT
+
+config BOARD_QEMU_X86_LAKEMONT
+	bool "QEMU x86 (Lakemont)"
+	depends on SOC_LAKEMONT
+	select QEMU_TARGET
+	select CPU_HAS_FPU
+	select HAS_COVERAGE_SUPPORT

boards/x86/qemu_x86/Kconfig.defconfig

@@ -35,3 +35,24 @@ config KERNEL_VM_SIZE
 	default 0x10000000 if ACPI
 
 endif # BOARD_QEMU_X86_64
+
+if BOARD_QEMU_X86_LAKEMONT
+
+config BUILD_OUTPUT_BIN
+	default n
+
+config BOARD
+	default "qemu_x86_lakemont"
+
+config KERNEL_VM_SIZE
+	default 0x400000
+
+config MULTIBOOT
+	# This is needed for QEMU to load the ELF image
+	default y
+
+config X86_PC_COMPATIBLE
+	# QEMU presents a PC-compatible machine
+	default y
+
+endif # BOARD_QEMU_X86_LAKEMONT

boards/x86/qemu_x86/qemu_x86_lakemont.dts

@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2021 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <mem.h>
+
+#ifndef DT_DRAM_BASE
+#define DT_DRAM_BASE		0
+#endif
+#ifndef DT_DRAM_SIZE
+#define DT_DRAM_SIZE		DT_SIZE_K(4096)
+#endif
+
+#include <lakemont.dtsi>
+
+/ {
+	model = "QEMU X86 (Lakemont) emulator";
+	compatible = "qemu,x86_lakemont_emulator";
+
+	aliases {
+		uart-0 = &uart0;
+	};
+
+	chosen {
+		zephyr,sram = &dram0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+
+	dram0: memory@0 {
+		device_type = "memory";
+		reg = <DT_DRAM_BASE DT_DRAM_SIZE>;
+	};
+
+	soc {
+		uart0: uart@3f8 {
+			compatible = "ns16550";
+			reg = <0x000003f8 0x100>;
+			label = "UART_0";
+			clock-frequency = <1843200>;
+			interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
+			interrupt-parent = <&intc>;
+			current-speed = <115200>;
+
+			status = "okay";
+		};
+
+		hpet: hpet@fed00000 {
+			label = "HPET";
+			compatible = "intel,hpet";
+			reg = <0xfed00000 0x400>;
+			interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
+			interrupt-parent = <&intc>;
+
+			status = "okay";
+		};
+	};
+};

boards/x86/qemu_x86/qemu_x86_lakemont.yaml

@@ -0,0 +1,13 @@
+identifier: qemu_x86_lakemont
+name: QEMU Emulation for X86 (Lakemont)
+type: qemu
+simulation: qemu
+arch: x86
+toolchain:
+  - zephyr
+  - xtools
+  - llvm
+testing:
+  default: true
+  only_tags:
+     - kernel

boards/x86/qemu_x86/qemu_x86_lakemont_defconfig

@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_LAKEMONT=y
+CONFIG_BOARD_QEMU_X86_LAKEMONT=y
+CONFIG_HPET_TIMER=y
+CONFIG_PIC_DISABLE=y
+CONFIG_LOAPIC=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000
+CONFIG_TEST_RANDOM_GENERATOR=y
+CONFIG_X86_MMU=y
+CONFIG_DEBUG_INFO=y
+CONFIG_SCHED_SCALABLE=y
+CONFIG_WAITQ_SCALABLE=y
+CONFIG_X86_VERY_EARLY_CONSOLE=y
+CONFIG_QEMU_ICOUNT_SHIFT=5

soc/x86/lakemont/soc.h

@@ -7,4 +7,9 @@
 #ifndef __SOC_H_
 #define __SOC_H_
 
+#ifdef CONFIG_BOARD_QEMU_X86_LAKEMONT
+/* QEMU uses IO port based UART */
+#define UART_NS16550_ACCESS_IOPORT 0x3f8
+#endif
+
 #endif /* __SOC_H_ */