From d1e830fe0d657ade703462e4a9f07333a074ecb7 Mon Sep 17 00:00:00 2001 From: Sudan Landge Date: Tue, 27 May 2025 11:32:41 +0100 Subject: [PATCH] boards: arm: add support for MPS4 Corstone-320 Add initial support for the MPS4 Corstone-320 platform, including board and SoC definitions. This platform features a Cortex-M85 CPU with an Ethos-U85 NPU and runs in simulation using the FVP_Corstone_SSE-320 Fixed Virtual Platform. Signed-off-by: Sudan Landge --- boards/arm/mps4/Kconfig.defconfig | 23 ++ boards/arm/mps4/Kconfig.mps4 | 6 + boards/arm/mps4/board.cmake | 45 ++++ boards/arm/mps4/board.yml | 10 + boards/arm/mps4/mps4_common.dtsi | 119 ++++++++++ .../arm/mps4/mps4_common_soc_peripheral.dtsi | 209 ++++++++++++++++++ boards/arm/mps4/mps4_corstone320_fvp.dts | 97 ++++++++ boards/arm/mps4/mps4_corstone320_fvp.yaml | 25 +++ .../arm/mps4/mps4_corstone320_fvp_defconfig | 19 ++ boards/arm/mps4/mps4_corstone320_fvp_ns.dts | 102 +++++++++ boards/arm/mps4/mps4_corstone320_fvp_ns.yaml | 15 ++ .../mps4/mps4_corstone320_fvp_ns_defconfig | 19 ++ soc/arm/mps4/CMakeLists.txt | 6 + soc/arm/mps4/Kconfig | 21 ++ soc/arm/mps4/Kconfig.defconfig | 11 + .../mps4/Kconfig.defconfig.mps4_corstone320 | 9 + soc/arm/mps4/Kconfig.soc | 18 ++ soc/arm/mps4/soc.h | 12 + soc/arm/soc.yml | 3 + 19 files changed, 769 insertions(+) create mode 100644 boards/arm/mps4/Kconfig.defconfig create mode 100644 boards/arm/mps4/Kconfig.mps4 create mode 100644 boards/arm/mps4/board.cmake create mode 100644 boards/arm/mps4/board.yml create mode 100644 boards/arm/mps4/mps4_common.dtsi create mode 100644 boards/arm/mps4/mps4_common_soc_peripheral.dtsi create mode 100644 boards/arm/mps4/mps4_corstone320_fvp.dts create mode 100644 boards/arm/mps4/mps4_corstone320_fvp.yaml create mode 100644 boards/arm/mps4/mps4_corstone320_fvp_defconfig create mode 100644 boards/arm/mps4/mps4_corstone320_fvp_ns.dts create mode 100644 boards/arm/mps4/mps4_corstone320_fvp_ns.yaml create mode 100644 boards/arm/mps4/mps4_corstone320_fvp_ns_defconfig create mode 100644 soc/arm/mps4/CMakeLists.txt create mode 100644 soc/arm/mps4/Kconfig create mode 100644 soc/arm/mps4/Kconfig.defconfig create mode 100644 soc/arm/mps4/Kconfig.defconfig.mps4_corstone320 create mode 100644 soc/arm/mps4/Kconfig.soc create mode 100644 soc/arm/mps4/soc.h diff --git a/boards/arm/mps4/Kconfig.defconfig b/boards/arm/mps4/Kconfig.defconfig new file mode 100644 index 00000000000..b4e98775386 --- /dev/null +++ b/boards/arm/mps4/Kconfig.defconfig @@ -0,0 +1,23 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MPS4_CORSTONE320_FVP + +if SERIAL + +config UART_INTERRUPT_DRIVEN + default y + +endif # SERIAL + +if ROMSTART_RELOCATION_ROM && BOARD_MPS4_CORSTONE320_FVP + +config ROMSTART_REGION_ADDRESS + default $(dt_nodelabel_reg_addr_hex,itcm) + +config ROMSTART_REGION_SIZE + default $(dt_nodelabel_reg_size_hex,itcm,0,k) + +endif + +endif diff --git a/boards/arm/mps4/Kconfig.mps4 b/boards/arm/mps4/Kconfig.mps4 new file mode 100644 index 00000000000..ffb494cf337 --- /dev/null +++ b/boards/arm/mps4/Kconfig.mps4 @@ -0,0 +1,6 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MPS4 + select SOC_SERIES_MPS4 + select SOC_MPS4_CORSTONE320 if BOARD_MPS4_CORSTONE320_FVP || BOARD_MPS4_CORSTONE320_FVP_NS diff --git a/boards/arm/mps4/board.cmake b/boards/arm/mps4/board.cmake new file mode 100644 index 00000000000..6497c65c426 --- /dev/null +++ b/boards/arm/mps4/board.cmake @@ -0,0 +1,45 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +# +# Default emulation: +# FVP is used by default for corstone320/fvp. +# + + +if(CONFIG_BOARD_MPS4_CORSTONE320_FVP OR CONFIG_BOARD_MPS4_CORSTONE320_FVP_NS) + set(SUPPORTED_EMU_PLATFORMS armfvp) + set(ARMFVP_BIN_NAME FVP_Corstone_SSE-320) + if(CONFIG_BOARD_MPS4_CORSTONE320_FVP) + set(ARMFVP_FLAGS + # default is '0x11000000' but should match cpu.INITSVTOR which is 0. + -C mps4_board.subsystem.iotss3_systemcontrol.INITSVTOR_RST=0 + # default is 0x8, this change is needed since we split flash into itcm + # and sram and it reduces the number of available mpu regions causing a + # few MPU tests to fail. + -C mps4_board.subsystem.cpu0.MPU_S=16 + ) + endif() +endif() + +if(CONFIG_BUILD_WITH_TFM) + set(ARMFVP_FLAGS ${ARMFVP_FLAGS} -a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex) +endif() + +# FVP Parameters +# -C indicate a config option in the form of: +# instance.parameter=value +# Run the FVP with --list-params to list all options +set(ARMFVP_FLAGS ${ARMFVP_FLAGS} + -C mps4_board.uart0.out_file=- + -C mps4_board.uart0.unbuffered_output=1 + -C mps4_board.uart1.out_file=- + -C mps4_board.uart1.unbuffered_output=1 + -C mps4_board.uart2.out_file=- + -C mps4_board.uart2.unbuffered_output=1 + -C mps4_board.visualisation.disable-visualisation=1 + -C mps4_board.telnetterminal0.start_telnet=0 + -C mps4_board.telnetterminal1.start_telnet=0 + -C mps4_board.telnetterminal2.start_telnet=0 + -C vis_hdlcd.disable_visualisation=1 + ) diff --git a/boards/arm/mps4/board.yml b/boards/arm/mps4/board.yml new file mode 100644 index 00000000000..8c2b411846f --- /dev/null +++ b/boards/arm/mps4/board.yml @@ -0,0 +1,10 @@ +board: + name: mps4 + full_name: MPS4 + vendor: arm + socs: + - name: 'corstone320' + variants: + - name: 'fvp' + variants: + - name: 'ns' diff --git a/boards/arm/mps4/mps4_common.dtsi b/boards/arm/mps4/mps4_common.dtsi new file mode 100644 index 00000000000..c2958fc5c07 --- /dev/null +++ b/boards/arm/mps4/mps4_common.dtsi @@ -0,0 +1,119 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* /dts-v1/; */ + +#include +#include +#include +#include +#include + +/ { + aliases { + led0 = &led_0; + led1 = &led_1; + sw0 = &user_button_0; + sw1 = &user_button_1; + }; + + leds { + compatible = "gpio-leds"; + + led_0: led_0 { + gpios = <&gpio_led0 0>; + label = "USERLED0"; + }; + + led_1: led_1 { + gpios = <&gpio_led0 1>; + label = "USERLED1"; + }; + + led_2: led_2 { + gpios = <&gpio_led0 2>; + label = "USERLED2"; + }; + + led_3: led_3 { + gpios = <&gpio_led0 3>; + label = "USERLED3"; + }; + + led_4: led_4 { + gpios = <&gpio_led0 4>; + label = "USERLED4"; + }; + + led_5: led_5 { + gpios = <&gpio_led0 5>; + label = "USERLED5"; + }; + + led_6: led_6 { + gpios = <&gpio_led0 6>; + label = "USERLED6"; + }; + + led_7: led_7 { + gpios = <&gpio_led0 7>; + label = "USERLED7"; + }; + + led_8: led_8 { + gpios = <&gpio_led0 8>; + label = "PB1LED"; + }; + + led_9: led_9 { + gpios = <&gpio_led0 9>; + label = "PB2LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button_0: button_0 { + label = "USERPB0"; + gpios = <&gpio_button 0>; + zephyr,code = ; + }; + + user_button_1: button_1 { + label = "USERPB1"; + gpios = <&gpio_button 1>; + zephyr,code = ; + }; + }; + + null_ptr_detect: null_ptr_detect@0 { + compatible = "zephyr,memory-region"; + /* 0 - CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE> */ + reg = <0x0 0x400>; + zephyr,memory-region = "NULL_PTR_DETECT"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_FLASH) )>; + }; + + /* DDR4 - 2G, alternates non-secure/secure every 256M */ + ddr4: memory@60000000 { + device_type = "memory"; + compatible = "zephyr,memory-region"; + reg = <0x60000000 DT_SIZE_M(256) + 0x70000000 DT_SIZE_M(256) + 0x80000000 DT_SIZE_M(256) + 0x90000000 DT_SIZE_M(256) + 0xa0000000 DT_SIZE_M(256) + 0xb0000000 DT_SIZE_M(256) + 0xc0000000 DT_SIZE_M(256) + 0xd0000000 DT_SIZE_M(256)>; + zephyr,memory-region = "DDR4"; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/boards/arm/mps4/mps4_common_soc_peripheral.dtsi b/boards/arm/mps4/mps4_common_soc_peripheral.dtsi new file mode 100644 index 00000000000..d94339e4c05 --- /dev/null +++ b/boards/arm/mps4/mps4_common_soc_peripheral.dtsi @@ -0,0 +1,209 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +sysclk: system-clock { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + #clock-cells = <0>; +}; + +gpio0: gpio@100000 { + compatible = "arm,cmsdk-gpio"; + reg = <0x100000 0x1000>; + interrupts = <69 3>; + gpio-controller; + #gpio-cells = <2>; +}; + +gpio1: gpio@101000 { + compatible = "arm,cmsdk-gpio"; + reg = <0x101000 0x1000>; + interrupts = <70 3>; + gpio-controller; + #gpio-cells = <2>; +}; + +gpio2: gpio@102000 { + compatible = "arm,cmsdk-gpio"; + reg = <0x102000 0x1000>; + interrupts = <71 3>; + gpio-controller; + #gpio-cells = <2>; +}; + +gpio3: gpio@103000 { + compatible = "arm,cmsdk-gpio"; + reg = <0x103000 0x1000>; + interrupts = <72 3>; + gpio-controller; + #gpio-cells = <2>; +}; + +eth0: eth@400000 { + /* Linux has "smsc,lan9115" */ + compatible = "smsc,lan9220"; + /* Actual reg range is ~0x200 */ + reg = <0x400000 0x100000>; + interrupts = <49 3>; +}; + +i2c_touch: i2c@8100000 { + compatible = "arm,versatile-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8100000 0x1000>; +}; + +i2c_audio_conf: i2c@8101000 { + compatible = "arm,versatile-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8101000 0x1000>; +}; + +spi_adc: spi@8102000 { + compatible = "arm,pl022"; + reg = <0x8102000 DT_SIZE_K(4)>; + interrupts = <53 3>; + interrupt-names = "shield_adc"; + clocks = <&sysclk>; + #address-cells = <1>; + #size-cells = <0>; +}; + +spi_shield0: spi@8103000 { + compatible = "arm,pl022"; + reg = <0x8103000 DT_SIZE_K(4)>; + interrupts = <54 3>; + interrupt-names = "shield0_spi"; + clocks = <&sysclk>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&spi3_default>; + pinctrl-names = "default"; +}; + +spi_shield1: spi@8104000 { + compatible = "arm,pl022"; + reg = <0x8104000 DT_SIZE_K(4)>; + interrupts = <55 3>; + interrupt-names = "shield1_spi"; + clocks = <&sysclk>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&spi4_default>; + pinctrl-names = "default"; +}; + +i2c_shield0: i2c@8105000 { + compatible = "arm,versatile-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8105000 0x1000>; + pinctrl-0 = <&sbcon2_default>; + pinctrl-names = "default"; +}; + +i2c_shield1: i2c@8106000 { + compatible = "arm,versatile-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8106000 0x1000>; + pinctrl-0 = <&sbcon3_default>; + pinctrl-names = "default"; +}; + +i2c_ddr4_eeprom: i2c@8108000 { + compatible = "arm,versatile-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8108000 0x1000>; +}; + +gpio_led0: mps4_fpgaio@8202000 { + compatible = "arm,mmio32-gpio"; + reg = <0x8202000 0x4>; + gpio-controller; + #gpio-cells = <1>; + ngpios = <8>; +}; + +gpio_button: mps4_fpgaio@8202008 { + compatible = "arm,mmio32-gpio"; + reg = <0x8202008 0x4>; + gpio-controller; + #gpio-cells = <1>; + ngpios = <2>; + direction-input; +}; + +gpio_misc: mps4_fpgaio@820204c { + compatible = "arm,mmio32-gpio"; + reg = <0x820204c 0x4>; + gpio-controller; + #gpio-cells = <1>; + ngpios = <3>; +}; + +uart0: uart@8203000 { + compatible = "arm,cmsdk-uart"; + reg = <0x8203000 0x1000>; + interrupts = <34 3 33 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; +}; + +uart1: uart@8204000 { + compatible = "arm,cmsdk-uart"; + reg = <0x8204000 0x1000>; + interrupts = <36 3 35 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; +}; + +uart2: uart@8205000 { + compatible = "arm,cmsdk-uart"; + reg = <0x8205000 0x1000>; + interrupts = <38 3 37 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; +}; + +uart3: uart@8206000 { + compatible = "arm,cmsdk-uart"; + reg = <0x8206000 0x1000>; + interrupts = <40 3 39 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; +}; + +uart4: uart@8207000 { + compatible = "arm,cmsdk-uart"; + reg = <0x8207000 0x1000>; + interrupts = <42 3 41 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; +}; + +uart5: uart@8208000 { + compatible = "arm,cmsdk-uart"; + status = "disabled"; + reg = <0x8208000 0x1000>; + interrupt-names = "tx", "rx"; + interrupts = <126 3 125 3>; + clocks = <&sysclk>; + current-speed = <115200>; +}; diff --git a/boards/arm/mps4/mps4_corstone320_fvp.dts b/boards/arm/mps4/mps4_corstone320_fvp.dts new file mode 100644 index 00000000000..98c87ce7ed7 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone320_fvp.dts @@ -0,0 +1,97 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + compatible = "arm,mps4-fvp"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram; + zephyr,flash = &isram; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m85"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + ethosu { + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&nvic>; + + ethosu0: ethosu@50004000 { + compatible = "arm,ethos-u"; + reg = <0x50004000>; + interrupts = <16 3>; + secure-enable; + privilege-enable; + status = "okay"; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@10000000 { /* alias @ 0x0 */ + compatible = "zephyr,memory-region"; + reg = <0x10000000 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@12000000 { /* alias @ 0x01000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x12000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@30000000 { /* alias @ 0x20000000 */ + compatible = "zephyr,memory-region"; + reg = <0x30000000 DT_SIZE_K(32)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@31000000 { /* alias @ 0x21000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x31000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; + }; + + soc { + peripheral@50000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000000 0x10000000>; + + #include "mps4_common_soc_peripheral.dtsi" + }; + }; +}; + +#include "mps4_common.dtsi" diff --git a/boards/arm/mps4/mps4_corstone320_fvp.yaml b/boards/arm/mps4/mps4_corstone320_fvp.yaml new file mode 100644 index 00000000000..624c8580812 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone320_fvp.yaml @@ -0,0 +1,25 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps4/corstone320/fvp +name: Arm MPS4-Corstone320-FVP +type: mcu +arch: arm +ram: 2048 +flash: 4096 +simulation: + - name: armfvp + exec: FVP_Corstone_SSE-320 +toolchain: + - gnuarmemb + - zephyr +supported: + - gpio +testing: + default: true + ignore_tags: + - drivers + - bluetooth + - net + - timer +vendor: arm diff --git a/boards/arm/mps4/mps4_corstone320_fvp_defconfig b/boards/arm/mps4/mps4_corstone320_fvp_defconfig new file mode 100644 index 00000000000..26d5a732e49 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone320_fvp_defconfig @@ -0,0 +1,19 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=y +# ROMSTART_REGION address and size are defined in Kconfig.defconfig +CONFIG_ROMSTART_RELOCATION_ROM=y diff --git a/boards/arm/mps4/mps4_corstone320_fvp_ns.dts b/boards/arm/mps4/mps4_corstone320_fvp_ns.dts new file mode 100644 index 00000000000..c511a7cc700 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone320_fvp_ns.dts @@ -0,0 +1,102 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + compatible = "arm,mps4-fvp"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &ram; + zephyr,flash = &code; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m85"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@0 { + compatible = "zephyr,memory-region"; + reg = <0x0 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@1000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x1000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@20000000 { + compatible = "zephyr,memory-region"; + reg = <0x20000000 DT_SIZE_K(512)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@21000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x21000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* The memory regions defined below must match what the TF-M + * project has defined for that board - a single image boot is + * assumed. Please see the memory layout in: + * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps4/corstone320/common/partition/flash_layout.h + */ + + code: memory@28080000 { + reg = <0x28080000 DT_SIZE_K(512)>; + }; + + ram: memory@21020000 { + reg = <0x21020000 DT_SIZE_M(1)>; + }; + }; + + soc { + peripheral@40000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000000 0x10000000>; + + #include "mps4_common_soc_peripheral.dtsi" + }; + }; +}; + +#include "mps4_common.dtsi" diff --git a/boards/arm/mps4/mps4_corstone320_fvp_ns.yaml b/boards/arm/mps4/mps4_corstone320_fvp_ns.yaml new file mode 100644 index 00000000000..45ee954a337 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone320_fvp_ns.yaml @@ -0,0 +1,15 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps4/corstone320/fvp/ns +name: Arm MPS4-Corstone320-FVP_ns +type: mcu +arch: arm +ram: 1024 +flash: 512 +toolchain: + - gnuarmemb + - zephyr +testing: + only_tags: + - trusted-firmware-m diff --git a/boards/arm/mps4/mps4_corstone320_fvp_ns_defconfig b/boards/arm/mps4/mps4_corstone320_fvp_ns_defconfig new file mode 100644 index 00000000000..d59d419011b --- /dev/null +++ b/boards/arm/mps4/mps4_corstone320_fvp_ns_defconfig @@ -0,0 +1,19 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Non-secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=n +CONFIG_TRUSTED_EXECUTION_NONSECURE=y +CONFIG_BUILD_WITH_TFM=y diff --git a/soc/arm/mps4/CMakeLists.txt b/soc/arm/mps4/CMakeLists.txt new file mode 100644 index 00000000000..1cc200dafbb --- /dev/null +++ b/soc/arm/mps4/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/mps4/Kconfig b/soc/arm/mps4/Kconfig new file mode 100644 index 00000000000..0054f715208 --- /dev/null +++ b/soc/arm/mps4/Kconfig @@ -0,0 +1,21 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MPS4 + select ARM + select GPIO_MMIO32 if GPIO + +config SOC_MPS4_CORSTONE320 + select CPU_CORTEX_M85 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARMV8_1_M_MVEI + select ARMV8_1_M_MVEF + select ARMV8_1_M_PMU + select ARM_MPU_PXN if ARM_MPU + +config ARMV8_1_M_PMU_EVENTCNT + int + default 8 if SOC_MPS4_CORSTONE320 diff --git a/soc/arm/mps4/Kconfig.defconfig b/soc/arm/mps4/Kconfig.defconfig new file mode 100644 index 00000000000..667eaadb35c --- /dev/null +++ b/soc/arm/mps4/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_MPS4 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(dt_nodelabel_path,sysclk),clock-frequency) + +rsource "Kconfig.defconfig.mps4*" + +endif # SOC_SERIES_MPS4 diff --git a/soc/arm/mps4/Kconfig.defconfig.mps4_corstone320 b/soc/arm/mps4/Kconfig.defconfig.mps4_corstone320 new file mode 100644 index 00000000000..f7348d7fcad --- /dev/null +++ b/soc/arm/mps4/Kconfig.defconfig.mps4_corstone320 @@ -0,0 +1,9 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MPS4_CORSTONE320 + +config NUM_IRQS + default 232 + +endif diff --git a/soc/arm/mps4/Kconfig.soc b/soc/arm/mps4/Kconfig.soc new file mode 100644 index 00000000000..a557d287f0e --- /dev/null +++ b/soc/arm/mps4/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MPS4 + bool + select SOC_FAMILY_ARM + help + Enable support for ARM MPS4 MCU Series + +config SOC_SERIES + default "mps4" if SOC_SERIES_MPS4 + +config SOC_MPS4_CORSTONE320 + bool + select SOC_SERIES_MPS4 + +config SOC + default "corstone320" if SOC_MPS4_CORSTONE320 diff --git a/soc/arm/mps4/soc.h b/soc/arm/mps4/soc.h new file mode 100644 index 00000000000..14ceadbd20a --- /dev/null +++ b/soc/arm/mps4/soc.h @@ -0,0 +1,12 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_H_ +#define _SOC_H_ + +#include + +#endif /* _SOC_H_ */ diff --git a/soc/arm/soc.yml b/soc/arm/soc.yml index 866f34dafd4..2caf077656a 100644 --- a/soc/arm/soc.yml +++ b/soc/arm/soc.yml @@ -15,6 +15,9 @@ family: socs: - name: corstone300 - name: corstone310 + - name: mps4 + socs: + - name: corstone320 - name: musca socs: - name: musca_b1