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soc: espressif: Fix psram0 node size and smh heap size calculation

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Fixing multiple things related to psram usage:
- fix conflicting psram0 dts node for all ESP32 SiP and SoC.
- fix dcache and icache area used in psram mapping.
- fix smh spiram heap allocations.
- add `espressif,esp32-psram` compatible to set psram0 size in dts.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit is contained in:
Marek Matej 2025-02-17 13:21:52 +01:00 • committed by Benjamin Cabé
commit d13fae97e4
43 changed files with 222 additions and 191 deletions
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69
soc/espressif/esp32s3/default.ld
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@ -17,7 +17,6 @@ procpu_dram_end = USER_DRAM_END - APPCPU_SRAM_SIZE;
procpu_iram_org = SRAM_USER_IRAM_START;
procpu_iram_len = procpu_iram_end - procpu_iram_org;
procpu_dram_org2 = ORIGIN(dram0_0_seg);
procpu_dram_org = SRAM1_DRAM_START;
procpu_dram_len = procpu_dram_end - procpu_dram_org;
@ -32,16 +31,20 @@ procpu_drom_org = DCACHE0_START;
procpu_drom_len = DCACHE0_SIZE - APPCPU_ROM_SIZE;
#if defined(CONFIG_ESP_SPIRAM)
procpu_extram_org = DCACHE0_START;
procpu_extram_len = CONFIG_ESP_SPIRAM_SIZE;
procpu_ext_dram_org = procpu_drom_org;
procpu_ext_dram_len = CONFIG_ESP_SPIRAM_SIZE;
procpu_ext_iram_org = procpu_irom_org;
procpu_ext_iram_len = CONFIG_ESP_SPIRAM_SIZE;
#endif
/* Aliases */
#define FLASH_CODE_REGION irom0_0_seg
#define RODATA_REGION drom0_0_seg
#define IRAM_REGION iram0_0_seg
#define RAMABLE_REGION dram0_0_seg
#define ROMABLE_REGION FLASH
#define FLASH_CODE_REGION irom0_0_seg
#define RODATA_REGION drom0_0_seg
#define IRAM_REGION iram0_0_seg
#define RAMABLE_REGION dram0_0_seg
#define EXT_DRAM_REGION ext_dram_seg
#define EXT_IRAM_REGION ext_iram_seg
#define ROMABLE_REGION FLASH
/* Zephyr macro re-definitions */
#undef GROUP_DATA_LINK_IN
@ -70,7 +73,8 @@ MEMORY
FLASH (R): org = 0x80, len = FLASH_SIZE - 0x80
#else
/* Make safety margin in the FLASH memory size so the
* (esp_img_header + (n*esp_seg_headers)) would fit */
* (esp_img_header + (n*esp_seg_headers)) would fit
*/
FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100
#endif /* CONFIG_BOOTLOADER_MCUBOOT */
@ -84,30 +88,28 @@ MEMORY
* A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in`
*/
#if defined(CONFIG_ESP_SPIRAM)
/* `ext_[id]ram_seg` and `drom0_0_seg` share the same bus and the address region.
/* `ext_dram_seg` and `drom0_0_seg` share the same bus and the address region.
* A dummy section is used to avoid overlap. See `.ext_ram.dummy` */
ext_dram_seg(RW): org = procpu_extram_org, len = procpu_extram_len
ext_iram_seg(RX): org = procpu_extram_org, len = procpu_extram_len
ext_dram_seg(RW): org = procpu_ext_dram_org, len = procpu_ext_dram_len
ext_iram_seg(RX): org = procpu_ext_iram_org, len = procpu_ext_iram_len
#endif
/* RTC fast memory (executable). Persists over deep sleep.
*/
/* RTC fast memory (executable). Persists over deep sleep. */
rtc_iram_seg(RWX): org = 0x600fe000, len = 0x2000 - CONFIG_RESERVE_RTC_MEM
/* We reduced the size of rtc_iram_seg by CONFIG_RESERVE_RTC_MEM value.
It reserves the amount of RTC fast memory that we use for this memory segment.
This segment is intended for keeping:
- (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
- (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
The aim of this is to keep data that will not be moved around and have a fixed address.
*/
* It reserves the amount of RTC fast memory that we use for this memory segment.
* This segment is intended for keeping:
* - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
* - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
* The aim of this is to keep data that will not be moved around and have a fixed address.
*/
#if (CONFIG_RESERVE_RTC_MEM > 0)
rtc_reserved_seg(RW): org = 0x600fe000 + 0x2000 - CONFIG_RESERVE_RTC_MEM,
len = CONFIG_RESERVE_RTC_MEM
#endif
/* RTC slow memory (data accessible). Persists over deep sleep.
*/
/* RTC slow memory (data accessible). Persists over deep sleep. */
rtc_slow_seg(RW): org = 0x50000000, len = 0x2000
#ifdef CONFIG_GEN_ISR_TABLES
@ -983,22 +985,17 @@ SECTIONS
/* --- START OF SPIRAM --- */
/**
* This section is required to skip flash rodata sections, because `ext_ram_seg`
* and `drom0_0_seg` are on the same bus
*/
#if defined(CONFIG_ESP_SPIRAM)
/* This section is required to skip flash rodata sections, because `ext_[id]ram_seg`
/* This section is required to skip flash rodata sections, because SPIRAM
* and `drom0_0_seg` are on the same bus */
.ext_ram.dummy (NOLOAD):
{
. = ADDR(.flash.rodata_end) - ORIGIN(ext_dram_seg);
. = ALIGN (CACHE_ALIGN);
} GROUP_LINK_IN(ext_dram_seg)
} GROUP_LINK_IN(EXT_DRAM_REGION)
/* This section holds .ext_ram.bss data, and will be put in PSRAM */
.ext_ram.bss (NOLOAD) :
.ext_ram.data (NOLOAD) :
{
_ext_ram_start = ABSOLUTE(.);
_ext_ram_noinit_start = ABSOLUTE(.);
@ -1009,7 +1006,9 @@ SECTIONS
*libsubsys__net__lib__config.a:(.noinit .noinit.*)
*libsubsys__net__ip.a:(.noinit .noinit.*)
*libsubsys__net.a:(.noinit .noinit.*)
#endif /* CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM */
#endif
. = ALIGN(16);
*(.ext_ram_noinit.*)
. = ALIGN(16);
_ext_ram_noinit_end = ABSOLUTE(.);
@ -1018,13 +1017,13 @@ SECTIONS
. = ALIGN(16);
_ext_ram_bss_end = ABSOLUTE(.);
_spiram_heap_start = ABSOLUTE(.);
. = . + CONFIG_ESP_SPIRAM_HEAP_SIZE - (_spiram_heap_start - _ext_ram_bss_start);
_ext_ram_heap_start = ABSOLUTE(.);
. += CONFIG_ESP_SPIRAM_HEAP_SIZE;
. = ALIGN(16);
_ext_ram_heap_end = ABSOLUTE(.);
_ext_ram_end = ABSOLUTE(.);
} GROUP_LINK_IN(ext_dram_seg)
} GROUP_LINK_IN(EXT_DRAM_REGION)
#endif /* CONFIG_ESP_SPIRAM */
/* --- END OF SPIRAM --- */