From d13fae97e4923b8ed4f4f8b437369f604cde583b Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Mon, 17 Feb 2025 13:21:52 +0100 Subject: [PATCH] soc: espressif: Fix psram0 node size and smh heap size calculation Fixing multiple things related to psram usage: - fix conflicting psram0 dts node for all ESP32 SiP and SoC. - fix dcache and icache area used in psram mapping. - fix smh spiram heap allocations. - add `espressif,esp32-psram` compatible to set psram0 size in dts. Signed-off-by: Marek Matej --- ...dafruit_qt_py_esp32s3_appcpu_psram.overlay | 3 +- ...dafruit_qt_py_esp32s3_procpu_psram.overlay | 3 +- .../m5stack_core2/m5stack_core2_procpu.dts | 3 +- .../espressif,esp32-psram.yaml | 13 ++++ dts/xtensa/espressif/esp32/esp32_common.dtsi | 31 ++++++--- .../espressif/esp32/esp32_d0wdr2_v3.dtsi | 3 +- .../espressif/esp32/esp32_pico_v3_02.dtsi | 3 +- .../espressif/esp32/esp32_wrover_e_n16r2.dtsi | 3 +- .../espressif/esp32/esp32_wrover_e_n16r4.dtsi | 3 +- .../espressif/esp32/esp32_wrover_e_n16r8.dtsi | 3 +- .../espressif/esp32/esp32_wrover_e_n4r2.dtsi | 3 +- .../espressif/esp32/esp32_wrover_e_n4r8.dtsi | 3 +- .../espressif/esp32/esp32_wrover_e_n8r2.dtsi | 3 +- .../espressif/esp32/esp32_wrover_e_n8r8.dtsi | 3 +- .../espressif/esp32s2/esp32s2_common.dtsi | 31 ++++++--- .../espressif/esp32s2/esp32s2_fn4r2.dtsi | 3 +- .../espressif/esp32s2/esp32s2_mini_n4r2.dtsi | 3 +- dts/xtensa/espressif/esp32s2/esp32s2_r2.dtsi | 3 +- .../espressif/esp32s2/esp32s2_solo_n4r2.dtsi | 3 +- .../esp32s2/esp32s2_wrover_n16r2.dtsi | 3 +- .../esp32s2/esp32s2_wrover_n4r2.dtsi | 3 +- .../esp32s2/esp32s2_wrover_n8r2.dtsi | 3 +- .../espressif/esp32s3/esp32s3_common.dtsi | 17 ++--- .../espressif/esp32s3/esp32s3_mini_n4r2.dtsi | 3 +- .../espressif/esp32s3/esp32s3_mini_n8.dtsi | 4 ++ .../espressif/esp32s3/esp32s3_pico_n8r2.dtsi | 3 +- .../espressif/esp32s3/esp32s3_pico_n8r8.dtsi | 3 +- dts/xtensa/espressif/esp32s3/esp32s3_r2.dtsi | 3 +- dts/xtensa/espressif/esp32s3/esp32s3_r8.dtsi | 3 +- dts/xtensa/espressif/esp32s3/esp32s3_r8v.dtsi | 3 +- .../esp32s3/esp32s3_wroom_n16r2.dtsi | 3 +- .../esp32s3/esp32s3_wroom_n16r8.dtsi | 3 +- .../espressif/esp32s3/esp32s3_wroom_n4r2.dtsi | 3 +- .../espressif/esp32s3/esp32s3_wroom_n4r8.dtsi | 3 +- .../espressif/esp32s3/esp32s3_wroom_n8r2.dtsi | 3 +- .../espressif/esp32s3/esp32s3_wroom_n8r8.dtsi | 3 +- soc/espressif/common/Kconfig.spiram | 16 +++-- soc/espressif/common/esp_psram.c | 9 +-- soc/espressif/esp32/default.ld | 53 +++++++------- soc/espressif/esp32/memory.h | 17 +++-- soc/espressif/esp32s2/default.ld | 43 +++++++----- soc/espressif/esp32s2/memory.h | 17 +++-- soc/espressif/esp32s3/default.ld | 69 +++++++++---------- 43 files changed, 222 insertions(+), 191 deletions(-) create mode 100644 dts/bindings/memory-controllers/espressif,esp32-psram.yaml diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay index ac1ec4af1b1..58eaee33a2b 100644 --- a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay @@ -27,8 +27,7 @@ /* 2MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; #include diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay index 5ab0be63c3f..cd9ca5f1dcf 100644 --- a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay @@ -27,8 +27,7 @@ /* 2MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; #include diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts index 554e1885488..1500087cca0 100644 --- a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts +++ b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts @@ -87,8 +87,7 @@ }; &psram0 { - reg = <0x3f800000 DT_SIZE_M(8)>; - status = "disabled"; + size = ; }; &uart0 { diff --git a/dts/bindings/memory-controllers/espressif,esp32-psram.yaml b/dts/bindings/memory-controllers/espressif,esp32-psram.yaml new file mode 100644 index 00000000000..d79a0723ff3 --- /dev/null +++ b/dts/bindings/memory-controllers/espressif,esp32-psram.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: ESP32 Family pseudo-static RAM controller + +compatible: "espressif,esp32-psram" + +include: base.yaml + +properties: + size: + type: int + required: true diff --git a/dts/xtensa/espressif/esp32/esp32_common.dtsi b/dts/xtensa/espressif/esp32/esp32_common.dtsi index b0eb8369049..1982deb1a40 100644 --- a/dts/xtensa/espressif/esp32/esp32_common.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_common.dtsi @@ -112,6 +112,29 @@ zephyr,memory-region = "SRAM2"; }; + dcache0: dcache0@3f400000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x3f400000 DT_SIZE_M(4)>; + zephyr,memory-region = "DCACHE0"; + }; + + dcache1: dcache1@3f800000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x3f800000 DT_SIZE_M(4)>; + zephyr,memory-region = "DCACHE1"; + + psram0: psram0 { + compatible = "espressif,esp32-psram"; + size = <0x0>; + }; + }; + + icache0: icache0@400d0000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x400d0000 DT_SIZE_K(11456)>; + zephyr,memory-region = "ICACHE0"; + }; + ipmmem0: memory@3ffe5230 { compatible = "mmio-sram"; reg = <0x3ffe5230 0x400>; @@ -189,14 +212,6 @@ }; }; - psram0: psram@3f800000 { - device_type = "memory"; - compatible = "mmio-sram"; - /* PSRAM size is specified in SOC/SIP dtsi */ - reg = <0x3f800000 DT_SIZE_M(2)>; - status = "disabled"; - }; - ipi0: ipi@3f4c0058 { compatible = "espressif,crosscore-interrupt"; reg = <0x3f4c0058 0x4>; diff --git a/dts/xtensa/espressif/esp32/esp32_d0wdr2_v3.dtsi b/dts/xtensa/espressif/esp32/esp32_d0wdr2_v3.dtsi index 2703231b821..c7180dd467d 100644 --- a/dts/xtensa/espressif/esp32/esp32_d0wdr2_v3.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_d0wdr2_v3.dtsi @@ -15,6 +15,5 @@ /* 2MB psram */ &psram0 { - reg = <0x3f800000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32/esp32_pico_v3_02.dtsi b/dts/xtensa/espressif/esp32/esp32_pico_v3_02.dtsi index 9d108bd4e57..03acd73f59e 100644 --- a/dts/xtensa/espressif/esp32/esp32_pico_v3_02.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_pico_v3_02.dtsi @@ -19,6 +19,5 @@ /* 2MB psram */ &psram0 { - reg = <0x3f800000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r2.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r2.dtsi index 4aa681336ac..2476afcacbd 100644 --- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r2.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r2.dtsi @@ -23,6 +23,5 @@ /* 2MB psram */ &psram0 { - reg = <0x3f800000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi index 37e2b62a004..1018cb453b0 100644 --- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi @@ -23,6 +23,5 @@ /* 4MB psram */ &psram0 { - reg = <0x3f800000 DT_SIZE_M(4)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r8.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r8.dtsi index 73ec91dca44..d6484cadb50 100644 --- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r8.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r8.dtsi @@ -23,6 +23,5 @@ /* 8MB psram */ &psram0 { - reg = <0x3f800000 DT_SIZE_M(8)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r2.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r2.dtsi index b0ab013feb3..9057bae18d3 100644 --- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r2.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r2.dtsi @@ -23,6 +23,5 @@ /* 2MB psram */ &psram0 { - reg = <0x3f800000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r8.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r8.dtsi index 87a2f8930ec..1171dc69882 100644 --- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r8.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r8.dtsi @@ -23,6 +23,5 @@ /* 8MB psram */ &psram0 { - reg = <0x3f800000 DT_SIZE_M(8)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r2.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r2.dtsi index 6b74a725ed4..281ebd835a5 100644 --- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r2.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r2.dtsi @@ -23,6 +23,5 @@ /* 2MB psram */ &psram0 { - reg = <0x3f800000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r8.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r8.dtsi index e5a12caae0c..19cf746989f 100644 --- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r8.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r8.dtsi @@ -24,6 +24,5 @@ /* 8MB flash */ &psram0 { - reg = <0x3f800000 DT_SIZE_M(8)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi index 32c2b92b763..da15a64059d 100644 --- a/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi +++ b/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi @@ -91,6 +91,29 @@ zephyr,memory-region = "SRAM1"; }; + dcache0: dcache0@3f000000 { + compatible = "zephyr,memory-region"; + reg = <0x3f000000 DT_SIZE_M(4)>; + zephyr,memory-region = "DCACHE0"; + }; + + dcache1: dcache1@3f500000 { + compatible = "zephyr,memory-region"; + reg = <0x3f500000 DT_SIZE_K(10752)>; + zephyr,memory-region = "DCACHE1"; + + psram0: psram0 { + compatible = "espressif,esp32-psram"; + size = <0x0>; + }; + }; + + icache0: icache0@40080000 { + compatible = "zephyr,memory-region"; + reg = <0x40080000 DT_SIZE_K(7680)>; + zephyr,memory-region = "ICACHE0"; + }; + intc: interrupt-controller@3f4c2000 { #interrupt-cells = <3>; #address-cells = <0>; @@ -142,14 +165,6 @@ }; }; - psram0: psram@3f500000 { - device_type = "memory"; - compatible = "mmio-sram"; - /* PSRAM size is specified in SOC/SIP dtsi */ - reg = <0x3f500000 DT_SIZE_M(2)>; - status = "disabled"; - }; - uart0: uart@3f400000 { compatible = "espressif,esp32-uart"; reg = <0x3f400000 0x400>; diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_fn4r2.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_fn4r2.dtsi index f3175a99233..fd8686b2334 100644 --- a/dts/xtensa/espressif/esp32s2/esp32s2_fn4r2.dtsi +++ b/dts/xtensa/espressif/esp32s2/esp32s2_fn4r2.dtsi @@ -13,6 +13,5 @@ /* 2MB psram */ &psram0 { - reg = <0x3f500000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_mini_n4r2.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_mini_n4r2.dtsi index 84e3b16cc39..fd8686b2334 100644 --- a/dts/xtensa/espressif/esp32s2/esp32s2_mini_n4r2.dtsi +++ b/dts/xtensa/espressif/esp32s2/esp32s2_mini_n4r2.dtsi @@ -13,6 +13,5 @@ /* 2MB psram */ &psram0 { - status = "okay"; - reg = <0x3f500000 DT_SIZE_M(2)>; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_r2.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_r2.dtsi index db004992e70..66d624e4e5c 100644 --- a/dts/xtensa/espressif/esp32s2/esp32s2_r2.dtsi +++ b/dts/xtensa/espressif/esp32s2/esp32s2_r2.dtsi @@ -8,6 +8,5 @@ /* 2MB psram */ &psram0 { - status = "okay"; - reg = <0x3f500000 DT_SIZE_M(2)>; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_solo_n4r2.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_solo_n4r2.dtsi index 84e3b16cc39..fd8686b2334 100644 --- a/dts/xtensa/espressif/esp32s2/esp32s2_solo_n4r2.dtsi +++ b/dts/xtensa/espressif/esp32s2/esp32s2_solo_n4r2.dtsi @@ -13,6 +13,5 @@ /* 2MB psram */ &psram0 { - status = "okay"; - reg = <0x3f500000 DT_SIZE_M(2)>; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n16r2.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n16r2.dtsi index 77645a3c2e0..053b0d6ee4a 100644 --- a/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n16r2.dtsi +++ b/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n16r2.dtsi @@ -13,6 +13,5 @@ /* 2MB psram */ &psram0 { - status = "okay"; - reg = <0x3f500000 DT_SIZE_M(2)>; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n4r2.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n4r2.dtsi index 84e3b16cc39..fd8686b2334 100644 --- a/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n4r2.dtsi +++ b/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n4r2.dtsi @@ -13,6 +13,5 @@ /* 2MB psram */ &psram0 { - status = "okay"; - reg = <0x3f500000 DT_SIZE_M(2)>; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n8r2.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n8r2.dtsi index 92d8775368e..5f3e9ecd713 100644 --- a/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n8r2.dtsi +++ b/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n8r2.dtsi @@ -13,6 +13,5 @@ /* 2MB psram */ &psram0 { - status = "okay"; - reg = <0x3f500000 DT_SIZE_M(2)>; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi index 95c935a1de6..1f4f046df4d 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi @@ -89,13 +89,18 @@ icache0: memory@42000000 { compatible = "zephyr,memory-region"; reg = <0x42000000 DT_SIZE_M(32)>; - zephyr,memory-region = "ICACHE"; + zephyr,memory-region = "ICACHE0"; }; dcache0: memory@3c000000 { compatible = "zephyr,memory-region"; reg = <0x3c000000 DT_SIZE_M(32)>; - zephyr,memory-region = "DCACHE"; + zephyr,memory-region = "DCACHE0"; + + psram0: psram0 { + compatible = "espressif,esp32-psram"; + size = <0x0>; + }; }; sram0: memory@40370000 { @@ -201,14 +206,6 @@ }; }; - psram0: psram@3c000000 { - device_type = "memory"; - compatible = "mmio-sram"; - /* PSRAM size is specified in SOC/SIP dtsi */ - reg = <0x3c000000 DT_SIZE_M(2)>; - status = "disabled"; - }; - uart0: uart@60000000 { compatible = "espressif,esp32-uart"; reg = <0x60000000 0x1000>; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_mini_n4r2.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_mini_n4r2.dtsi index b8f733a3c54..843c999f525 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_mini_n4r2.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_mini_n4r2.dtsi @@ -13,6 +13,5 @@ /* 2MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_mini_n8.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_mini_n8.dtsi index 4b2e7404282..5639f2bd921 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_mini_n8.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_mini_n8.dtsi @@ -10,3 +10,7 @@ &flash0 { reg = <0x0 DT_SIZE_M(8)>; }; + +&psram0 { + size = ; +}; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r2.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r2.dtsi index b77169f172b..31c631bbde0 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r2.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r2.dtsi @@ -13,6 +13,5 @@ /* 2MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r8.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r8.dtsi index 34ec0ec5ac1..a3de8d6faa6 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r8.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r8.dtsi @@ -13,6 +13,5 @@ /* 8MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(8)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_r2.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_r2.dtsi index 187a214078f..df68b4852cb 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_r2.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_r2.dtsi @@ -8,6 +8,5 @@ /* 2MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_r8.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_r8.dtsi index 29a21140630..3b192040f04 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_r8.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_r8.dtsi @@ -8,6 +8,5 @@ /* 8MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(8)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_r8v.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_r8v.dtsi index 29a21140630..3b192040f04 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_r8v.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_r8v.dtsi @@ -8,6 +8,5 @@ /* 8MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(8)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r2.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r2.dtsi index c4c0929063d..e3a4bf89b90 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r2.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r2.dtsi @@ -13,6 +13,5 @@ /* 2MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r8.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r8.dtsi index 102fd94ec12..45cbd4cf0b1 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r8.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r8.dtsi @@ -13,6 +13,5 @@ /* 8MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(8)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r2.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r2.dtsi index b8f733a3c54..843c999f525 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r2.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r2.dtsi @@ -13,6 +13,5 @@ /* 2MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r8.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r8.dtsi index b17d9f9223b..429044da2b1 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r8.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r8.dtsi @@ -13,6 +13,5 @@ /* 8MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(8)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r2.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r2.dtsi index b77169f172b..31c631bbde0 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r2.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r2.dtsi @@ -13,6 +13,5 @@ /* 2MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(2)>; - status = "okay"; + size = ; }; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r8.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r8.dtsi index 34ec0ec5ac1..a3de8d6faa6 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r8.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r8.dtsi @@ -13,6 +13,5 @@ /* 8MB psram */ &psram0 { - reg = <0x3c000000 DT_SIZE_M(8)>; - status = "okay"; + size = ; }; diff --git a/soc/espressif/common/Kconfig.spiram b/soc/espressif/common/Kconfig.spiram index 1c209839a7a..1222b9261d9 100644 --- a/soc/espressif/common/Kconfig.spiram +++ b/soc/espressif/common/Kconfig.spiram @@ -3,6 +3,8 @@ if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 +ESP32_PSRAM0_NODE_PATH := $(dt_nodelabel_path,psram0) + config ESP_SPIRAM bool "Support for external, SPI-connected RAM" default n if MCUBOOT @@ -48,26 +50,26 @@ choice SPIRAM_TYPE config SPIRAM_TYPE_ESPPSRAM16 bool "ESP-PSRAM16 or APS1604" - depends on SPIRAM_MODE_QUAD + depends on SPIRAM_MODE_QUAD && (ESP_SPIRAM_SIZE = 2097152) config SPIRAM_TYPE_ESPPSRAM32 bool "ESP-PSRAM32 or IS25WP032" - depends on SPIRAM_MODE_QUAD + depends on SPIRAM_MODE_QUAD && (ESP_SPIRAM_SIZE = 4194304) config SPIRAM_TYPE_ESPPSRAM64 bool "ESP-PSRAM64, LY68L6400 or APS6408" + depends on (ESP_SPIRAM_SIZE = 8388608) endchoice # SPIRAM_TYPE config ESP_SPIRAM_SIZE int "Size of SPIRAM part" - default 2097152 if SPIRAM_TYPE_ESPPSRAM16 - default 4194304 if SPIRAM_TYPE_ESPPSRAM32 - default 8388608 if SPIRAM_TYPE_ESPPSRAM64 + default $(dt_node_int_prop_int,$(ESP32_PSRAM0_NODE_PATH),size) if $(dt_nodelabel_enabled,psram0) + default 0 help Specify size of SPIRAM part. - NOTE: If SPIRAM size is greater than 4MB, only - lower 4MB can be allocated using k_malloc(). + NOTE: In ESP32, if SPIRAM size is greater than 4MB, + only lower 4MB can be allocated using k_malloc(). choice SPIRAM_SPEED prompt "Set RAM clock speed" diff --git a/soc/espressif/common/esp_psram.c b/soc/espressif/common/esp_psram.c index 37e814fcc76..aa3b01c8b93 100644 --- a/soc/espressif/common/esp_psram.c +++ b/soc/espressif/common/esp_psram.c @@ -10,22 +10,19 @@ #include #include -#define PSRAM_ADDR (DT_REG_ADDR(DT_NODELABEL(psram0))) - -extern int _spiram_heap_start; extern int _ext_ram_bss_start; extern int _ext_ram_bss_end; +extern int _ext_ram_heap_start; struct shared_multi_heap_region smh_psram = { - .addr = (uintptr_t)&_spiram_heap_start, - .size = CONFIG_ESP_SPIRAM_SIZE, + .addr = (uintptr_t)&_ext_ram_heap_start, + .size = CONFIG_ESP_SPIRAM_HEAP_SIZE, .attr = SMH_REG_ATTR_EXTERNAL, }; int esp_psram_smh_init(void) { shared_multi_heap_pool_init(); - smh_psram.size = CONFIG_ESP_SPIRAM_SIZE - ((int)&_spiram_heap_start - PSRAM_ADDR); return shared_multi_heap_add(&smh_psram, NULL); } diff --git a/soc/espressif/esp32/default.ld b/soc/espressif/esp32/default.ld index 44c74d4ce89..9d210a8040f 100644 --- a/soc/espressif/esp32/default.ld +++ b/soc/espressif/esp32/default.ld @@ -24,13 +24,23 @@ procpu_dram_len = SRAM2_DRAM_USER_SIZE - CONFIG_ESP32_BT_RESERVE_DRAM; user_dram_2_seg_org = SRAM1_DRAM_USER_START; user_dram_2_seg_len = SRAM1_USER_SIZE; +procpu_irom_org = ICACHE0_START; +procpu_irom_len = ICACHE0_SIZE; +procpu_drom_org = DCACHE0_START; +procpu_drom_len = DCACHE0_SIZE; + +#ifdef CONFIG_ESP_SPIRAM +procpu_ext_ram_org = DCACHE1_START; +procpu_ext_ram_len = DCACHE1_SIZE; +#endif + /* Aliases */ -#define FLASH_CODE_REGION irom0_0_seg -#define RODATA_REGION drom0_0_seg -#define IRAM_REGION iram0_0_seg -#define DRAM_REGION dram0_0_seg -#define RAMABLE_REGION dram0_0_seg -#define ROMABLE_REGION FLASH +#define FLASH_CODE_REGION irom0_0_seg +#define RODATA_REGION drom0_0_seg +#define IRAM_REGION iram0_0_seg +#define DRAM_REGION dram0_0_seg +#define RAMABLE_REGION dram0_0_seg +#define ROMABLE_REGION FLASH #undef GROUP_DATA_LINK_IN #define GROUP_DATA_LINK_IN(vregion, lregion) > vregion AT > lregion @@ -58,33 +68,34 @@ MEMORY FLASH (R): org = 0x80, len = FLASH_SIZE - 0x80 #else /* Make safety margin in the FLASH memory size so the - * (esp_img_header + (n*esp_seg_headers)) would fit */ + * (esp_img_header + (n*esp_seg_headers)) would fit + */ FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100 #endif /* CONFIG_BOOTLOADER_MCUBOOT */ iram0_0_seg(RX): org = procpu_iram_org, len = procpu_iram_len dram0_0_seg(RW): org = procpu_dram_org, len = procpu_dram_len - irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN - drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN + irom0_0_seg(RX): org = procpu_irom_org, len = procpu_irom_len + drom0_0_seg(R): org = procpu_drom_org, len = procpu_drom_len rtc_iram_seg(RWX): org = 0x400c0000, len = 0x2000 rtc_slow_seg(RW): org = 0x50000000, len = 0x2000 - CONFIG_RESERVE_RTC_MEM rtc_data_seg(RW): org = 0x3ff80000, len = 0x2000 /* We reduced the size of rtc_slow_seg by CONFIG_RESERVE_RTC_MEM value. - It reserves the amount of RTC slow memory that we use for this memory segment. - This segment is intended for keeping rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). - The aim of this is to keep data that will not be moved around and have a fixed address. - org = 0x50000000 + 0x2000 - CONFIG_RESERVE_RTC_MEM - */ + * It reserves the amount of RTC slow memory that we use for this memory segment. + * This segment is intended for keeping rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). + * The aim of this is to keep data that will not be moved around and have a fixed address. + * org = 0x50000000 + 0x2000 - CONFIG_RESERVE_RTC_MEM + */ #if (CONFIG_RESERVE_RTC_MEM > 0) rtc_slow_reserved_seg(RW): org = 0x50000000 + 0x2000 - CONFIG_RESERVE_RTC_MEM, len = CONFIG_RESERVE_RTC_MEM #endif #ifdef CONFIG_ESP_SPIRAM - ext_ram_seg(RW): org = 0x3f800000, len = CONFIG_ESP_SPIRAM_SIZE + ext_ram_seg(RW): org = procpu_ext_ram_org, len = procpu_ext_ram_len #endif /* CONFIG_ESP_SPIRAM */ #ifdef CONFIG_GEN_ISR_TABLES @@ -813,25 +824,21 @@ SECTIONS *libsubsys__net__lib__config.a:(.noinit .noinit.*) *libsubsys__net__ip.a:(.noinit .noinit.*) *libsubsys__net.a:(.noinit .noinit.*) -#endif /* CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM */ +#endif . = ALIGN(16); - *(.ext_ram_noinit*) - *(.ext_ram_noinit.*) - . = ALIGN(16); _ext_ram_noinit_end = ABSOLUTE(.); _ext_ram_bss_start = ABSOLUTE(.); - *(.ext_ram.bss*) - . = ALIGN(16); _ext_ram_bss_end = ABSOLUTE(.); - _spiram_heap_start = ABSOLUTE(.); + _ext_ram_heap_start = ABSOLUTE(.); . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; - . = ALIGN(4); + . = ALIGN(16); + _ext_ram_heap_end = ABSOLUTE(.); _ext_ram_end = ABSOLUTE(.); } GROUP_LINK_IN(ext_ram_seg) diff --git a/soc/espressif/esp32/memory.h b/soc/espressif/esp32/memory.h index 67da219f2d1..deffc8e4204 100644 --- a/soc/espressif/esp32/memory.h +++ b/soc/espressif/esp32/memory.h @@ -87,16 +87,19 @@ #define APPCPU_SRAM_SIZE (APPCPU_IRAM_SIZE + APPCPU_DRAM_SIZE) +/* Cached memories */ +#define ICACHE0_START DT_REG_ADDR(DT_NODELABEL(icache0)) +#define ICACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(icache0)) +#define DCACHE0_START DT_REG_ADDR(DT_NODELABEL(dcache0)) +#define DCACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(dcache0)) +#define DCACHE1_START DT_REG_ADDR(DT_NODELABEL(dcache1)) +#define DCACHE1_SIZE DT_REG_SIZE(DT_NODELABEL(dcache1)) + +#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE + /* Flash */ #ifdef CONFIG_FLASH_SIZE #define FLASH_SIZE CONFIG_FLASH_SIZE #else #define FLASH_SIZE 0x400000 #endif - -/* Cached memories */ -#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE -#define IROM_SEG_ORG 0x400d0000 -#define IROM_SEG_LEN (FLASH_SIZE - 0x1000) -#define DROM_SEG_ORG 0x3f400000 -#define DROM_SEG_LEN (FLASH_SIZE - 0x1000) diff --git a/soc/espressif/esp32s2/default.ld b/soc/espressif/esp32s2/default.ld index a9ca15c0dca..085f3e70114 100644 --- a/soc/espressif/esp32s2/default.ld +++ b/soc/espressif/esp32s2/default.ld @@ -23,12 +23,22 @@ user_iram_end = BOOTLOADER_IRAM_LOADER_SEG_START; #endif /* User available SRAM memory segments */ -user_iram_seg_org = SRAM_IRAM_START + SRAM_CACHE_SIZE; -user_dram_seg_org = SRAM_DRAM_START + SRAM_CACHE_SIZE; +user_iram_org = SRAM_IRAM_START + SRAM_CACHE_SIZE; +user_dram_org = SRAM_DRAM_START + SRAM_CACHE_SIZE; user_dram_end = user_iram_end - IRAM_DRAM_OFFSET; -user_sram_size = (user_dram_end - user_dram_seg_org); -user_iram_seg_len = user_sram_size; -user_dram_seg_len = user_sram_size; +user_sram_size = (user_dram_end - user_dram_org); +user_iram_len = user_sram_size; +user_dram_len = user_sram_size; + +user_irom_org = ICACHE0_START; +user_irom_len = ICACHE0_SIZE; +user_drom_org = DCACHE0_START; +user_drom_len = DCACHE0_SIZE; + +#if defined(CONFIG_ESP_SPIRAM) +ext_ram_org = DCACHE1_START; +ext_ram_len = DCACHE1_SIZE; +#endif /* Aliases */ #define FLASH_CODE_REGION irom0_0_seg @@ -67,11 +77,11 @@ MEMORY FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100 #endif - iram0_0_seg(RX): org = user_iram_seg_org, len = user_iram_seg_len - dram0_0_seg(RW): org = user_dram_seg_org, len = user_dram_seg_len + iram0_0_seg(RX): org = user_iram_org, len = user_iram_len + dram0_0_seg(RW): org = user_dram_org, len = user_dram_len - irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN - drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN + irom0_0_seg(RX): org = user_irom_org, len = user_irom_len + drom0_0_seg(R): org = user_drom_org, len = user_drom_len rtc_iram_seg(RWX): org = 0x40070000, len = 0x2000 - CONFIG_RESERVE_RTC_MEM rtc_slow_seg(RW): org = 0x50000000, len = 0x2000 @@ -90,7 +100,7 @@ MEMORY #endif #ifdef CONFIG_ESP_SPIRAM - ext_ram_seg(RW): org = 0x3f800000, len = CONFIG_ESP_SPIRAM_SIZE /* OR 0x780000 */ + ext_ram_seg(RW): org = ext_ram_org, len = ext_ram_len #endif /* CONFIG_ESP_SPIRAM */ #ifdef CONFIG_GEN_ISR_TABLES @@ -551,7 +561,7 @@ SECTIONS /* This section is required to skip .iram0.text area because iram0_0_seg and * dram0_0_seg reflect the same address space on different buses. */ - . = ORIGIN(dram0_0_seg) + MAX(_iram_end, user_iram_seg_org) - user_iram_seg_org; + . = ORIGIN(dram0_0_seg) + MAX(_iram_end, user_iram_org) - user_iram_org; . = ALIGN(4) + 16; } GROUP_LINK_IN(RAMABLE_REGION) @@ -791,24 +801,21 @@ SECTIONS *libsubsys__net__lib__config.a:(.noinit .noinit.*) *libsubsys__net__ip.a:(.noinit .noinit.*) *libsubsys__net.a:(.noinit .noinit.*) -#endif /* CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM */ +#endif . = ALIGN(16); - *(.ext_ram_noinit*) - *(.ext_ram_noinit.*) - . = ALIGN(16); _ext_ram_noinit_end = ABSOLUTE(.); _ext_ram_bss_start = ABSOLUTE(.); - *(.ext_ram.bss*) - . = ALIGN(16); _ext_ram_bss_end = ABSOLUTE(.); - _spiram_heap_start = ABSOLUTE(.); + _ext_ram_heap_start = ABSOLUTE(.); . += CONFIG_ESP_SPIRAM_HEAP_SIZE; + . = ALIGN(16); + _ext_ram_heap_end = ABSOLUTE(.); _ext_ram_end = ABSOLUTE(.); } GROUP_LINK_IN(ext_ram_seg) diff --git a/soc/espressif/esp32s2/memory.h b/soc/espressif/esp32s2/memory.h index 4b6e8a17c36..92d49dd3dc4 100644 --- a/soc/espressif/esp32s2/memory.h +++ b/soc/espressif/esp32s2/memory.h @@ -53,16 +53,19 @@ #define BOOTLOADER_DRAM_SEG_START \ (BOOTLOADER_IRAM_SEG_START - BOOTLOADER_DRAM_SEG_LEN - IRAM_DRAM_OFFSET) +/* Cached memories */ +#define ICACHE0_START DT_REG_ADDR(DT_NODELABEL(icache0)) +#define ICACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(icache0)) +#define DCACHE0_START DT_REG_ADDR(DT_NODELABEL(dcache0)) +#define DCACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(dcache0)) +#define DCACHE1_START DT_REG_ADDR(DT_NODELABEL(dcache1)) +#define DCACHE1_SIZE DT_REG_SIZE(DT_NODELABEL(dcache1)) + +#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE + /* Flash */ #ifdef CONFIG_FLASH_SIZE #define FLASH_SIZE CONFIG_FLASH_SIZE #else #define FLASH_SIZE 0x400000 #endif - -/* Cached memories */ -#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE -#define IROM_SEG_ORG 0x40080000 -#define IROM_SEG_LEN 0x780000 -#define DROM_SEG_ORG 0x3f000000 -#define DROM_SEG_LEN FLASH_SIZE diff --git a/soc/espressif/esp32s3/default.ld b/soc/espressif/esp32s3/default.ld index 79f8af91bd5..e1c87a2de7a 100644 --- a/soc/espressif/esp32s3/default.ld +++ b/soc/espressif/esp32s3/default.ld @@ -17,7 +17,6 @@ procpu_dram_end = USER_DRAM_END - APPCPU_SRAM_SIZE; procpu_iram_org = SRAM_USER_IRAM_START; procpu_iram_len = procpu_iram_end - procpu_iram_org; -procpu_dram_org2 = ORIGIN(dram0_0_seg); procpu_dram_org = SRAM1_DRAM_START; procpu_dram_len = procpu_dram_end - procpu_dram_org; @@ -32,16 +31,20 @@ procpu_drom_org = DCACHE0_START; procpu_drom_len = DCACHE0_SIZE - APPCPU_ROM_SIZE; #if defined(CONFIG_ESP_SPIRAM) -procpu_extram_org = DCACHE0_START; -procpu_extram_len = CONFIG_ESP_SPIRAM_SIZE; +procpu_ext_dram_org = procpu_drom_org; +procpu_ext_dram_len = CONFIG_ESP_SPIRAM_SIZE; +procpu_ext_iram_org = procpu_irom_org; +procpu_ext_iram_len = CONFIG_ESP_SPIRAM_SIZE; #endif /* Aliases */ -#define FLASH_CODE_REGION irom0_0_seg -#define RODATA_REGION drom0_0_seg -#define IRAM_REGION iram0_0_seg -#define RAMABLE_REGION dram0_0_seg -#define ROMABLE_REGION FLASH +#define FLASH_CODE_REGION irom0_0_seg +#define RODATA_REGION drom0_0_seg +#define IRAM_REGION iram0_0_seg +#define RAMABLE_REGION dram0_0_seg +#define EXT_DRAM_REGION ext_dram_seg +#define EXT_IRAM_REGION ext_iram_seg +#define ROMABLE_REGION FLASH /* Zephyr macro re-definitions */ #undef GROUP_DATA_LINK_IN @@ -70,7 +73,8 @@ MEMORY FLASH (R): org = 0x80, len = FLASH_SIZE - 0x80 #else /* Make safety margin in the FLASH memory size so the - * (esp_img_header + (n*esp_seg_headers)) would fit */ + * (esp_img_header + (n*esp_seg_headers)) would fit + */ FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100 #endif /* CONFIG_BOOTLOADER_MCUBOOT */ @@ -84,30 +88,28 @@ MEMORY * A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in` */ #if defined(CONFIG_ESP_SPIRAM) - /* `ext_[id]ram_seg` and `drom0_0_seg` share the same bus and the address region. + /* `ext_dram_seg` and `drom0_0_seg` share the same bus and the address region. * A dummy section is used to avoid overlap. See `.ext_ram.dummy` */ - ext_dram_seg(RW): org = procpu_extram_org, len = procpu_extram_len - ext_iram_seg(RX): org = procpu_extram_org, len = procpu_extram_len + ext_dram_seg(RW): org = procpu_ext_dram_org, len = procpu_ext_dram_len + ext_iram_seg(RX): org = procpu_ext_iram_org, len = procpu_ext_iram_len #endif - /* RTC fast memory (executable). Persists over deep sleep. - */ + /* RTC fast memory (executable). Persists over deep sleep. */ rtc_iram_seg(RWX): org = 0x600fe000, len = 0x2000 - CONFIG_RESERVE_RTC_MEM /* We reduced the size of rtc_iram_seg by CONFIG_RESERVE_RTC_MEM value. - It reserves the amount of RTC fast memory that we use for this memory segment. - This segment is intended for keeping: - - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). - - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on). - The aim of this is to keep data that will not be moved around and have a fixed address. - */ + * It reserves the amount of RTC fast memory that we use for this memory segment. + * This segment is intended for keeping: + * - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). + * - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on). + * The aim of this is to keep data that will not be moved around and have a fixed address. + */ #if (CONFIG_RESERVE_RTC_MEM > 0) rtc_reserved_seg(RW): org = 0x600fe000 + 0x2000 - CONFIG_RESERVE_RTC_MEM, len = CONFIG_RESERVE_RTC_MEM #endif - /* RTC slow memory (data accessible). Persists over deep sleep. - */ + /* RTC slow memory (data accessible). Persists over deep sleep. */ rtc_slow_seg(RW): org = 0x50000000, len = 0x2000 #ifdef CONFIG_GEN_ISR_TABLES @@ -983,22 +985,17 @@ SECTIONS /* --- START OF SPIRAM --- */ - /** - * This section is required to skip flash rodata sections, because `ext_ram_seg` - * and `drom0_0_seg` are on the same bus - */ #if defined(CONFIG_ESP_SPIRAM) - - /* This section is required to skip flash rodata sections, because `ext_[id]ram_seg` + /* This section is required to skip flash rodata sections, because SPIRAM * and `drom0_0_seg` are on the same bus */ .ext_ram.dummy (NOLOAD): { . = ADDR(.flash.rodata_end) - ORIGIN(ext_dram_seg); . = ALIGN (CACHE_ALIGN); - } GROUP_LINK_IN(ext_dram_seg) + } GROUP_LINK_IN(EXT_DRAM_REGION) /* This section holds .ext_ram.bss data, and will be put in PSRAM */ - .ext_ram.bss (NOLOAD) : + .ext_ram.data (NOLOAD) : { _ext_ram_start = ABSOLUTE(.); _ext_ram_noinit_start = ABSOLUTE(.); @@ -1009,7 +1006,9 @@ SECTIONS *libsubsys__net__lib__config.a:(.noinit .noinit.*) *libsubsys__net__ip.a:(.noinit .noinit.*) *libsubsys__net.a:(.noinit .noinit.*) -#endif /* CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM */ +#endif + . = ALIGN(16); + *(.ext_ram_noinit.*) . = ALIGN(16); _ext_ram_noinit_end = ABSOLUTE(.); @@ -1018,13 +1017,13 @@ SECTIONS . = ALIGN(16); _ext_ram_bss_end = ABSOLUTE(.); - _spiram_heap_start = ABSOLUTE(.); - . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE - (_spiram_heap_start - _ext_ram_bss_start); + _ext_ram_heap_start = ABSOLUTE(.); + . += CONFIG_ESP_SPIRAM_HEAP_SIZE; . = ALIGN(16); + _ext_ram_heap_end = ABSOLUTE(.); _ext_ram_end = ABSOLUTE(.); - } GROUP_LINK_IN(ext_dram_seg) - + } GROUP_LINK_IN(EXT_DRAM_REGION) #endif /* CONFIG_ESP_SPIRAM */ /* --- END OF SPIRAM --- */