soc: espressif: Fix psram0 node size and smh heap size calculation
Fixing multiple things related to psram usage: - fix conflicting psram0 dts node for all ESP32 SiP and SoC. - fix dcache and icache area used in psram mapping. - fix smh spiram heap allocations. - add `espressif,esp32-psram` compatible to set psram0 size in dts. Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit is contained in:
Marek Matej
Benjamin Cabé
parent
259e890039
commit
d13fae97e4
43 changed files with 222 additions and 191 deletions
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@ -3,6 +3,8 @@
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if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
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ESP32_PSRAM0_NODE_PATH := $(dt_nodelabel_path,psram0)
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config ESP_SPIRAM
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bool "Support for external, SPI-connected RAM"
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default n if MCUBOOT
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@ -48,26 +50,26 @@ choice SPIRAM_TYPE
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config SPIRAM_TYPE_ESPPSRAM16
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bool "ESP-PSRAM16 or APS1604"
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depends on SPIRAM_MODE_QUAD
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depends on SPIRAM_MODE_QUAD && (ESP_SPIRAM_SIZE = 2097152)
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config SPIRAM_TYPE_ESPPSRAM32
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bool "ESP-PSRAM32 or IS25WP032"
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depends on SPIRAM_MODE_QUAD
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depends on SPIRAM_MODE_QUAD && (ESP_SPIRAM_SIZE = 4194304)
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config SPIRAM_TYPE_ESPPSRAM64
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bool "ESP-PSRAM64, LY68L6400 or APS6408"
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depends on (ESP_SPIRAM_SIZE = 8388608)
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endchoice # SPIRAM_TYPE
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config ESP_SPIRAM_SIZE
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int "Size of SPIRAM part"
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default 2097152 if SPIRAM_TYPE_ESPPSRAM16
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default 4194304 if SPIRAM_TYPE_ESPPSRAM32
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default 8388608 if SPIRAM_TYPE_ESPPSRAM64
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default $(dt_node_int_prop_int,$(ESP32_PSRAM0_NODE_PATH),size) if $(dt_nodelabel_enabled,psram0)
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default 0
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help
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Specify size of SPIRAM part.
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NOTE: If SPIRAM size is greater than 4MB, only
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lower 4MB can be allocated using k_malloc().
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NOTE: In ESP32, if SPIRAM size is greater than 4MB,
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only lower 4MB can be allocated using k_malloc().
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choice SPIRAM_SPEED
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prompt "Set RAM clock speed"
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@ -10,22 +10,19 @@
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#include <esp_private/esp_psram_extram.h>
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#include <zephyr/multi_heap/shared_multi_heap.h>
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#define PSRAM_ADDR (DT_REG_ADDR(DT_NODELABEL(psram0)))
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extern int _spiram_heap_start;
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extern int _ext_ram_bss_start;
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extern int _ext_ram_bss_end;
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extern int _ext_ram_heap_start;
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struct shared_multi_heap_region smh_psram = {
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.addr = (uintptr_t)&_spiram_heap_start,
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.size = CONFIG_ESP_SPIRAM_SIZE,
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.addr = (uintptr_t)&_ext_ram_heap_start,
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.size = CONFIG_ESP_SPIRAM_HEAP_SIZE,
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.attr = SMH_REG_ATTR_EXTERNAL,
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};
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int esp_psram_smh_init(void)
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{
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shared_multi_heap_pool_init();
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smh_psram.size = CONFIG_ESP_SPIRAM_SIZE - ((int)&_spiram_heap_start - PSRAM_ADDR);
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return shared_multi_heap_add(&smh_psram, NULL);
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}
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@ -24,13 +24,23 @@ procpu_dram_len = SRAM2_DRAM_USER_SIZE - CONFIG_ESP32_BT_RESERVE_DRAM;
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user_dram_2_seg_org = SRAM1_DRAM_USER_START;
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user_dram_2_seg_len = SRAM1_USER_SIZE;
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procpu_irom_org = ICACHE0_START;
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procpu_irom_len = ICACHE0_SIZE;
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procpu_drom_org = DCACHE0_START;
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procpu_drom_len = DCACHE0_SIZE;
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#ifdef CONFIG_ESP_SPIRAM
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procpu_ext_ram_org = DCACHE1_START;
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procpu_ext_ram_len = DCACHE1_SIZE;
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#endif
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/* Aliases */
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#define FLASH_CODE_REGION irom0_0_seg
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#define RODATA_REGION drom0_0_seg
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#define IRAM_REGION iram0_0_seg
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#define DRAM_REGION dram0_0_seg
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#define RAMABLE_REGION dram0_0_seg
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#define ROMABLE_REGION FLASH
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#define FLASH_CODE_REGION irom0_0_seg
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#define RODATA_REGION drom0_0_seg
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#define IRAM_REGION iram0_0_seg
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#define DRAM_REGION dram0_0_seg
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#define RAMABLE_REGION dram0_0_seg
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#define ROMABLE_REGION FLASH
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#undef GROUP_DATA_LINK_IN
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#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion AT > lregion
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@ -58,33 +68,34 @@ MEMORY
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FLASH (R): org = 0x80, len = FLASH_SIZE - 0x80
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#else
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/* Make safety margin in the FLASH memory size so the
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* (esp_img_header + (n*esp_seg_headers)) would fit */
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* (esp_img_header + (n*esp_seg_headers)) would fit
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*/
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FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100
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#endif /* CONFIG_BOOTLOADER_MCUBOOT */
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iram0_0_seg(RX): org = procpu_iram_org, len = procpu_iram_len
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dram0_0_seg(RW): org = procpu_dram_org, len = procpu_dram_len
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irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
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drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN
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irom0_0_seg(RX): org = procpu_irom_org, len = procpu_irom_len
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drom0_0_seg(R): org = procpu_drom_org, len = procpu_drom_len
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rtc_iram_seg(RWX): org = 0x400c0000, len = 0x2000
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rtc_slow_seg(RW): org = 0x50000000, len = 0x2000 - CONFIG_RESERVE_RTC_MEM
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rtc_data_seg(RW): org = 0x3ff80000, len = 0x2000
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/* We reduced the size of rtc_slow_seg by CONFIG_RESERVE_RTC_MEM value.
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It reserves the amount of RTC slow memory that we use for this memory segment.
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This segment is intended for keeping rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
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The aim of this is to keep data that will not be moved around and have a fixed address.
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org = 0x50000000 + 0x2000 - CONFIG_RESERVE_RTC_MEM
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*/
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* It reserves the amount of RTC slow memory that we use for this memory segment.
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* This segment is intended for keeping rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
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* The aim of this is to keep data that will not be moved around and have a fixed address.
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* org = 0x50000000 + 0x2000 - CONFIG_RESERVE_RTC_MEM
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*/
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#if (CONFIG_RESERVE_RTC_MEM > 0)
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rtc_slow_reserved_seg(RW): org = 0x50000000 + 0x2000 - CONFIG_RESERVE_RTC_MEM,
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len = CONFIG_RESERVE_RTC_MEM
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#endif
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#ifdef CONFIG_ESP_SPIRAM
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ext_ram_seg(RW): org = 0x3f800000, len = CONFIG_ESP_SPIRAM_SIZE
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ext_ram_seg(RW): org = procpu_ext_ram_org, len = procpu_ext_ram_len
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#endif /* CONFIG_ESP_SPIRAM */
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#ifdef CONFIG_GEN_ISR_TABLES
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@ -813,25 +824,21 @@ SECTIONS
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*libsubsys__net__lib__config.a:(.noinit .noinit.*)
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*libsubsys__net__ip.a:(.noinit .noinit.*)
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*libsubsys__net.a:(.noinit .noinit.*)
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#endif /* CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM */
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#endif
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. = ALIGN(16);
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*(.ext_ram_noinit*)
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*(.ext_ram_noinit.*)
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. = ALIGN(16);
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_ext_ram_noinit_end = ABSOLUTE(.);
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_ext_ram_bss_start = ABSOLUTE(.);
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*(.ext_ram.bss*)
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. = ALIGN(16);
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_ext_ram_bss_end = ABSOLUTE(.);
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_spiram_heap_start = ABSOLUTE(.);
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_ext_ram_heap_start = ABSOLUTE(.);
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. = . + CONFIG_ESP_SPIRAM_HEAP_SIZE;
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. = ALIGN(4);
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. = ALIGN(16);
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_ext_ram_heap_end = ABSOLUTE(.);
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_ext_ram_end = ABSOLUTE(.);
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} GROUP_LINK_IN(ext_ram_seg)
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@ -87,16 +87,19 @@
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#define APPCPU_SRAM_SIZE (APPCPU_IRAM_SIZE + APPCPU_DRAM_SIZE)
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/* Cached memories */
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#define ICACHE0_START DT_REG_ADDR(DT_NODELABEL(icache0))
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#define ICACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(icache0))
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#define DCACHE0_START DT_REG_ADDR(DT_NODELABEL(dcache0))
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#define DCACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(dcache0))
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#define DCACHE1_START DT_REG_ADDR(DT_NODELABEL(dcache1))
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#define DCACHE1_SIZE DT_REG_SIZE(DT_NODELABEL(dcache1))
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#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE
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/* Flash */
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#ifdef CONFIG_FLASH_SIZE
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#define FLASH_SIZE CONFIG_FLASH_SIZE
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#else
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#define FLASH_SIZE 0x400000
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#endif
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/* Cached memories */
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#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE
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#define IROM_SEG_ORG 0x400d0000
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#define IROM_SEG_LEN (FLASH_SIZE - 0x1000)
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#define DROM_SEG_ORG 0x3f400000
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#define DROM_SEG_LEN (FLASH_SIZE - 0x1000)
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@ -23,12 +23,22 @@ user_iram_end = BOOTLOADER_IRAM_LOADER_SEG_START;
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#endif
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/* User available SRAM memory segments */
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user_iram_seg_org = SRAM_IRAM_START + SRAM_CACHE_SIZE;
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user_dram_seg_org = SRAM_DRAM_START + SRAM_CACHE_SIZE;
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user_iram_org = SRAM_IRAM_START + SRAM_CACHE_SIZE;
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user_dram_org = SRAM_DRAM_START + SRAM_CACHE_SIZE;
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user_dram_end = user_iram_end - IRAM_DRAM_OFFSET;
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user_sram_size = (user_dram_end - user_dram_seg_org);
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user_iram_seg_len = user_sram_size;
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user_dram_seg_len = user_sram_size;
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user_sram_size = (user_dram_end - user_dram_org);
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user_iram_len = user_sram_size;
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user_dram_len = user_sram_size;
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user_irom_org = ICACHE0_START;
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user_irom_len = ICACHE0_SIZE;
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user_drom_org = DCACHE0_START;
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user_drom_len = DCACHE0_SIZE;
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#if defined(CONFIG_ESP_SPIRAM)
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ext_ram_org = DCACHE1_START;
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ext_ram_len = DCACHE1_SIZE;
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#endif
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/* Aliases */
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#define FLASH_CODE_REGION irom0_0_seg
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@ -67,11 +77,11 @@ MEMORY
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FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100
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#endif
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iram0_0_seg(RX): org = user_iram_seg_org, len = user_iram_seg_len
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dram0_0_seg(RW): org = user_dram_seg_org, len = user_dram_seg_len
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iram0_0_seg(RX): org = user_iram_org, len = user_iram_len
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dram0_0_seg(RW): org = user_dram_org, len = user_dram_len
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irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
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drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN
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irom0_0_seg(RX): org = user_irom_org, len = user_irom_len
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drom0_0_seg(R): org = user_drom_org, len = user_drom_len
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rtc_iram_seg(RWX): org = 0x40070000, len = 0x2000 - CONFIG_RESERVE_RTC_MEM
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rtc_slow_seg(RW): org = 0x50000000, len = 0x2000
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@ -90,7 +100,7 @@ MEMORY
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#endif
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#ifdef CONFIG_ESP_SPIRAM
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ext_ram_seg(RW): org = 0x3f800000, len = CONFIG_ESP_SPIRAM_SIZE /* OR 0x780000 */
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ext_ram_seg(RW): org = ext_ram_org, len = ext_ram_len
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#endif /* CONFIG_ESP_SPIRAM */
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#ifdef CONFIG_GEN_ISR_TABLES
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@ -551,7 +561,7 @@ SECTIONS
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/* This section is required to skip .iram0.text area because iram0_0_seg and
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* dram0_0_seg reflect the same address space on different buses.
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*/
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. = ORIGIN(dram0_0_seg) + MAX(_iram_end, user_iram_seg_org) - user_iram_seg_org;
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. = ORIGIN(dram0_0_seg) + MAX(_iram_end, user_iram_org) - user_iram_org;
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. = ALIGN(4) + 16;
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} GROUP_LINK_IN(RAMABLE_REGION)
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@ -791,24 +801,21 @@ SECTIONS
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*libsubsys__net__lib__config.a:(.noinit .noinit.*)
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*libsubsys__net__ip.a:(.noinit .noinit.*)
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*libsubsys__net.a:(.noinit .noinit.*)
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#endif /* CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM */
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#endif
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. = ALIGN(16);
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*(.ext_ram_noinit*)
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*(.ext_ram_noinit.*)
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. = ALIGN(16);
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_ext_ram_noinit_end = ABSOLUTE(.);
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_ext_ram_bss_start = ABSOLUTE(.);
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*(.ext_ram.bss*)
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. = ALIGN(16);
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_ext_ram_bss_end = ABSOLUTE(.);
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_spiram_heap_start = ABSOLUTE(.);
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_ext_ram_heap_start = ABSOLUTE(.);
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. += CONFIG_ESP_SPIRAM_HEAP_SIZE;
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. = ALIGN(16);
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_ext_ram_heap_end = ABSOLUTE(.);
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_ext_ram_end = ABSOLUTE(.);
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} GROUP_LINK_IN(ext_ram_seg)
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@ -53,16 +53,19 @@
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#define BOOTLOADER_DRAM_SEG_START \
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(BOOTLOADER_IRAM_SEG_START - BOOTLOADER_DRAM_SEG_LEN - IRAM_DRAM_OFFSET)
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/* Cached memories */
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#define ICACHE0_START DT_REG_ADDR(DT_NODELABEL(icache0))
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#define ICACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(icache0))
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#define DCACHE0_START DT_REG_ADDR(DT_NODELABEL(dcache0))
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#define DCACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(dcache0))
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#define DCACHE1_START DT_REG_ADDR(DT_NODELABEL(dcache1))
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#define DCACHE1_SIZE DT_REG_SIZE(DT_NODELABEL(dcache1))
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#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE
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/* Flash */
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#ifdef CONFIG_FLASH_SIZE
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#define FLASH_SIZE CONFIG_FLASH_SIZE
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#else
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#define FLASH_SIZE 0x400000
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#endif
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/* Cached memories */
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#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE
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#define IROM_SEG_ORG 0x40080000
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#define IROM_SEG_LEN 0x780000
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#define DROM_SEG_ORG 0x3f000000
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#define DROM_SEG_LEN FLASH_SIZE
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@ -17,7 +17,6 @@ procpu_dram_end = USER_DRAM_END - APPCPU_SRAM_SIZE;
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procpu_iram_org = SRAM_USER_IRAM_START;
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procpu_iram_len = procpu_iram_end - procpu_iram_org;
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procpu_dram_org2 = ORIGIN(dram0_0_seg);
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procpu_dram_org = SRAM1_DRAM_START;
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procpu_dram_len = procpu_dram_end - procpu_dram_org;
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@ -32,16 +31,20 @@ procpu_drom_org = DCACHE0_START;
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procpu_drom_len = DCACHE0_SIZE - APPCPU_ROM_SIZE;
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#if defined(CONFIG_ESP_SPIRAM)
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procpu_extram_org = DCACHE0_START;
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procpu_extram_len = CONFIG_ESP_SPIRAM_SIZE;
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procpu_ext_dram_org = procpu_drom_org;
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procpu_ext_dram_len = CONFIG_ESP_SPIRAM_SIZE;
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procpu_ext_iram_org = procpu_irom_org;
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procpu_ext_iram_len = CONFIG_ESP_SPIRAM_SIZE;
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#endif
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/* Aliases */
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#define FLASH_CODE_REGION irom0_0_seg
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#define RODATA_REGION drom0_0_seg
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#define IRAM_REGION iram0_0_seg
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#define RAMABLE_REGION dram0_0_seg
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#define ROMABLE_REGION FLASH
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#define FLASH_CODE_REGION irom0_0_seg
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#define RODATA_REGION drom0_0_seg
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#define IRAM_REGION iram0_0_seg
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#define RAMABLE_REGION dram0_0_seg
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#define EXT_DRAM_REGION ext_dram_seg
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#define EXT_IRAM_REGION ext_iram_seg
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#define ROMABLE_REGION FLASH
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/* Zephyr macro re-definitions */
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#undef GROUP_DATA_LINK_IN
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@ -70,7 +73,8 @@ MEMORY
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FLASH (R): org = 0x80, len = FLASH_SIZE - 0x80
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#else
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/* Make safety margin in the FLASH memory size so the
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* (esp_img_header + (n*esp_seg_headers)) would fit */
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* (esp_img_header + (n*esp_seg_headers)) would fit
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*/
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FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100
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#endif /* CONFIG_BOOTLOADER_MCUBOOT */
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@ -84,30 +88,28 @@ MEMORY
|
|||
* A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in`
|
||||
*/
|
||||
#if defined(CONFIG_ESP_SPIRAM)
|
||||
/* `ext_[id]ram_seg` and `drom0_0_seg` share the same bus and the address region.
|
||||
/* `ext_dram_seg` and `drom0_0_seg` share the same bus and the address region.
|
||||
* A dummy section is used to avoid overlap. See `.ext_ram.dummy` */
|
||||
ext_dram_seg(RW): org = procpu_extram_org, len = procpu_extram_len
|
||||
ext_iram_seg(RX): org = procpu_extram_org, len = procpu_extram_len
|
||||
ext_dram_seg(RW): org = procpu_ext_dram_org, len = procpu_ext_dram_len
|
||||
ext_iram_seg(RX): org = procpu_ext_iram_org, len = procpu_ext_iram_len
|
||||
#endif
|
||||
|
||||
/* RTC fast memory (executable). Persists over deep sleep.
|
||||
*/
|
||||
/* RTC fast memory (executable). Persists over deep sleep. */
|
||||
rtc_iram_seg(RWX): org = 0x600fe000, len = 0x2000 - CONFIG_RESERVE_RTC_MEM
|
||||
|
||||
/* We reduced the size of rtc_iram_seg by CONFIG_RESERVE_RTC_MEM value.
|
||||
It reserves the amount of RTC fast memory that we use for this memory segment.
|
||||
This segment is intended for keeping:
|
||||
- (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
|
||||
- (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
|
||||
The aim of this is to keep data that will not be moved around and have a fixed address.
|
||||
*/
|
||||
* It reserves the amount of RTC fast memory that we use for this memory segment.
|
||||
* This segment is intended for keeping:
|
||||
* - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
|
||||
* - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
|
||||
* The aim of this is to keep data that will not be moved around and have a fixed address.
|
||||
*/
|
||||
#if (CONFIG_RESERVE_RTC_MEM > 0)
|
||||
rtc_reserved_seg(RW): org = 0x600fe000 + 0x2000 - CONFIG_RESERVE_RTC_MEM,
|
||||
len = CONFIG_RESERVE_RTC_MEM
|
||||
#endif
|
||||
|
||||
/* RTC slow memory (data accessible). Persists over deep sleep.
|
||||
*/
|
||||
/* RTC slow memory (data accessible). Persists over deep sleep. */
|
||||
rtc_slow_seg(RW): org = 0x50000000, len = 0x2000
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
|
|
@ -983,22 +985,17 @@ SECTIONS
|
|||
|
||||
/* --- START OF SPIRAM --- */
|
||||
|
||||
/**
|
||||
* This section is required to skip flash rodata sections, because `ext_ram_seg`
|
||||
* and `drom0_0_seg` are on the same bus
|
||||
*/
|
||||
#if defined(CONFIG_ESP_SPIRAM)
|
||||
|
||||
/* This section is required to skip flash rodata sections, because `ext_[id]ram_seg`
|
||||
/* This section is required to skip flash rodata sections, because SPIRAM
|
||||
* and `drom0_0_seg` are on the same bus */
|
||||
.ext_ram.dummy (NOLOAD):
|
||||
{
|
||||
. = ADDR(.flash.rodata_end) - ORIGIN(ext_dram_seg);
|
||||
. = ALIGN (CACHE_ALIGN);
|
||||
} GROUP_LINK_IN(ext_dram_seg)
|
||||
} GROUP_LINK_IN(EXT_DRAM_REGION)
|
||||
|
||||
/* This section holds .ext_ram.bss data, and will be put in PSRAM */
|
||||
.ext_ram.bss (NOLOAD) :
|
||||
.ext_ram.data (NOLOAD) :
|
||||
{
|
||||
_ext_ram_start = ABSOLUTE(.);
|
||||
_ext_ram_noinit_start = ABSOLUTE(.);
|
||||
|
|
@ -1009,7 +1006,9 @@ SECTIONS
|
|||
*libsubsys__net__lib__config.a:(.noinit .noinit.*)
|
||||
*libsubsys__net__ip.a:(.noinit .noinit.*)
|
||||
*libsubsys__net.a:(.noinit .noinit.*)
|
||||
#endif /* CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM */
|
||||
#endif
|
||||
. = ALIGN(16);
|
||||
*(.ext_ram_noinit.*)
|
||||
. = ALIGN(16);
|
||||
_ext_ram_noinit_end = ABSOLUTE(.);
|
||||
|
||||
|
|
@ -1018,13 +1017,13 @@ SECTIONS
|
|||
. = ALIGN(16);
|
||||
_ext_ram_bss_end = ABSOLUTE(.);
|
||||
|
||||
_spiram_heap_start = ABSOLUTE(.);
|
||||
. = . + CONFIG_ESP_SPIRAM_HEAP_SIZE - (_spiram_heap_start - _ext_ram_bss_start);
|
||||
_ext_ram_heap_start = ABSOLUTE(.);
|
||||
. += CONFIG_ESP_SPIRAM_HEAP_SIZE;
|
||||
. = ALIGN(16);
|
||||
_ext_ram_heap_end = ABSOLUTE(.);
|
||||
|
||||
_ext_ram_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(ext_dram_seg)
|
||||
|
||||
} GROUP_LINK_IN(EXT_DRAM_REGION)
|
||||
#endif /* CONFIG_ESP_SPIRAM */
|
||||
|
||||
/* --- END OF SPIRAM --- */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue