From d0e488e0718820504bb83ae945251b87cf12bbeb Mon Sep 17 00:00:00 2001 From: Alvis Sun Date: Sun, 10 Dec 2023 19:37:57 -0800 Subject: [PATCH] drivers: pinctrl: npcx: add pinctrl driver support for npck3 As title. Signed-off-by: Alvis Sun --- drivers/pinctrl/Kconfig.npcx | 7 ++++++- drivers/pinctrl/pinctrl_npcx.c | 13 +++++++++++++ dts/arm/nuvoton/npck/npck.dtsi | 2 +- .../pinctrl/nuvoton,npcx-pinctrl-npckn.yaml | 9 +++++++++ soc/nuvoton/npcx/common/scfg.c | 12 ++++++++++++ 5 files changed, 41 insertions(+), 2 deletions(-) create mode 100644 dts/bindings/pinctrl/nuvoton,npcx-pinctrl-npckn.yaml diff --git a/drivers/pinctrl/Kconfig.npcx b/drivers/pinctrl/Kconfig.npcx index d6ea4e71533..0e8106e4111 100644 --- a/drivers/pinctrl/Kconfig.npcx +++ b/drivers/pinctrl/Kconfig.npcx @@ -3,7 +3,6 @@ # Copyright (c) 2022 Nuvoton Technology Corporation. # SPDX-License-Identifier: Apache-2.0 - config PINCTRL_NPCX bool "Nuvoton NPCX embedded controller (EC) pin controller driver" default y @@ -11,3 +10,9 @@ config PINCTRL_NPCX help This option enables the pin controller driver for NPCX family of processors. + +config PINCTRL_NPCX_EX + bool "Extended NPCX driver support" + default y if DT_HAS_NUVOTON_NPCX_PINCTRL_NPCKN_ENABLED + help + This option enables the extended driver for NPCKN variant of processors. diff --git a/drivers/pinctrl/pinctrl_npcx.c b/drivers/pinctrl/pinctrl_npcx.c index 373a7158cfc..158dc87c9a4 100644 --- a/drivers/pinctrl/pinctrl_npcx.c +++ b/drivers/pinctrl/pinctrl_npcx.c @@ -139,11 +139,24 @@ static void npcx_psl_input_detection_configure(const pinctrl_soc_pin_t *pin) } /* Configure detection mode of PSL input pads */ +#if defined(CONFIG_PINCTRL_NPCX_EX) + if (pin->flags.psl_in_mode == NPCX_PSL_IN_MODE_EDGE) { + inst_glue->PSL_CTS3 |= BIT(psl_in->port); + } else { + inst_glue->PSL_CTS3 &= ~BIT(psl_in->port); + } + + /* Clear event bits */ + inst_glue->PSL_CTS |= BIT(psl_in->port); + inst_glue->PSL_IN_POS |= BIT(psl_in->port); + inst_glue->PSL_IN_NEG |= BIT(psl_in->port); +#else if (pin->flags.psl_in_mode == NPCX_PSL_IN_MODE_EDGE) { inst_glue->PSL_CTS |= NPCX_PSL_CTS_MODE_BIT(psl_in->port); } else { inst_glue->PSL_CTS &= ~NPCX_PSL_CTS_MODE_BIT(psl_in->port); } +#endif /* CONFIG_PINCTRL_NPCX_EX */ } static void npcx_device_control_configure(const pinctrl_soc_pin_t *pin) diff --git a/dts/arm/nuvoton/npck/npck.dtsi b/dts/arm/nuvoton/npck/npck.dtsi index b8d49194d58..074ac9c496f 100644 --- a/dts/arm/nuvoton/npck/npck.dtsi +++ b/dts/arm/nuvoton/npck/npck.dtsi @@ -56,7 +56,7 @@ * Then, the user can override the pin control options at the board level. */ pinctrl: pinctrl { - compatible = "nuvoton,npcx-pinctrl"; + compatible = "nuvoton,npcx-pinctrl", "nuvoton,npcx-pinctrl-npckn"; status = "okay"; }; diff --git a/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-npckn.yaml b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-npckn.yaml new file mode 100644 index 00000000000..0618d87c3c9 --- /dev/null +++ b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-npckn.yaml @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +description: | + Nuvoton npcx pinctrl for npckn variant + +compatible: "nuvoton,npcx-pinctrl-npckn" + +include: nuvoton,npcx-pinctrl.yaml diff --git a/soc/nuvoton/npcx/common/scfg.c b/soc/nuvoton/npcx/common/scfg.c index b29d7356b55..955a560f04a 100644 --- a/soc/nuvoton/npcx/common/scfg.c +++ b/soc/nuvoton/npcx/common/scfg.c @@ -98,6 +98,7 @@ void npcx_pinctrl_i2c_port_sel(int controller, int port) { struct glue_reg *const inst_glue = HAL_GLUE_INST(); + /* Set SMB_SEL bit to select port 1, otherwise select port 0 */ if (port != 0) { inst_glue->SMB_SEL |= BIT(controller); } else { @@ -138,10 +139,17 @@ int npcx_pinctrl_flash_write_protect_set(void) { struct scfg_reg *inst_scfg = HAL_SFCG_INST(); +#if defined(CONFIG_PINCTRL_NPCX_EX) + inst_scfg->DEV_CTL3 |= BIT(NPCX_DEV_CTL3_WP_IF); + if (!IS_BIT_SET(inst_scfg->DEV_CTL3, NPCX_DEV_CTL3_WP_IF)) { + return -EIO; + } +#else inst_scfg->DEV_CTL4 |= BIT(NPCX_DEV_CTL4_WP_IF); if (!IS_BIT_SET(inst_scfg->DEV_CTL4, NPCX_DEV_CTL4_WP_IF)) { return -EIO; } +#endif return 0; } @@ -150,7 +158,11 @@ bool npcx_pinctrl_flash_write_protect_is_set(void) { struct scfg_reg *inst_scfg = HAL_SFCG_INST(); +#if defined(CONFIG_PINCTRL_NPCX_EX) + return IS_BIT_SET(inst_scfg->DEV_CTL3, NPCX_DEV_CTL3_WP_IF); +#else return IS_BIT_SET(inst_scfg->DEV_CTL4, NPCX_DEV_CTL4_WP_IF); +#endif } void npcx_host_interface_sel(enum npcx_hif_type hif_type)