board: npcx: add npcx9m6f_evb board.

Introduce the npcx9m6f_evb board driver. NPCX9M6F_EVB board is a
development platform to evaluate the Nuvoton NPCX9 series
microcontrollers. This board needs to be mated with part number
NPCX996F.

It also includes:
 1. Add CONFIG_BOARD_NPCX9M6F_EVB definition for adc test suite.
 2. Add npcx7m6f_evb.overlay file for gpio test suite.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>

boards/arm/npcx9m6f_evb/Kconfig.board

@@ -0,0 +1,6 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NPCX9M6F_EVB
+	bool "Nuvoton NPCX9M6F EVB Development board"
+	depends on SOC_NPCX9M6F

boards/arm/npcx9m6f_evb/Kconfig.defconfig

@@ -0,0 +1,12 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NPCX9M6F_EVB
+
+config BOARD
+	default "npcx9m6f_evb"
+
+endif # BOARD_NPCX9M6F_EVB
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 1000

boards/arm/npcx9m6f_evb/board.cmake

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set(NPCX_IMAGE_FILE  ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}_${BOARD}.bin)
+
+set(TARGET_IMAGE_ADDR  ${CONFIG_FLASH_BASE_ADDRESS})
+set(TARGET_IMAGE_SIZE  ${CONFIG_FLASH_SIZE})
+
+board_set_flasher_ifnset(openocd)
+board_set_debugger_ifnset(openocd)
+
+board_finalize_runner_args(openocd
+  --cmd-load "flash_npcx ${MONITOR_IMAGE_FILE} ${NPCX_IMAGE_FILE} ${TARGET_IMAGE_ADDR} ${TARGET_IMAGE_SIZE}"
+  --cmd-verify "verify_npcx"
+  )

boards/arm/npcx9m6f_evb/doc/index.rst

@@ -0,0 +1,112 @@
+.. _npcx9m6f_evb:
+
+NPCX9M6F_EVB
+###################
+
+Overview
+********
+
+The NPCX9M6F_EVB kit is a development platform to evaluate the
+Nuvoton NPCX9 series microcontrollers. This board needs to be mated with
+part number NPCX996F.
+
+.. image:: ./npcx9m6f_evb.png
+     :width: 800px
+     :align: center
+     :alt: NPCX9M6F Evaluation Board
+
+Hardware
+********
+
+- ARM Cortex-M4F Processor
+- 256 KB RAM and 64 KB boot ROM
+- ADC & GPIO headers
+- UART0 and UART1
+- FAN PWM interface
+- Jtag interface
+- Intel Modular Embedded Controller Card (MECC) headers
+
+Supported Features
+==================
+
+The following features are supported:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| ADC       | on-chip    | adc controller                      |
++-----------+------------+-------------------------------------+
+| CLOCK     | on-chip    | reset and clock control             |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| I2C       | on-chip    | i2c port/controller                 |
++-----------+------------+-------------------------------------+
+| PINMUX    | on-chip    | pinmux                              |
++-----------+------------+-------------------------------------+
+| PM        | on-chip    | power management                    |
++-----------+------------+-------------------------------------+
+| PSL       | on-chip    | power switch logic                  |
++-----------+------------+-------------------------------------+
+| PWM       | on-chip    | pulse width modulator               |
++-----------+------------+-------------------------------------+
+| TACH      | on-chip    | tachometer sensor                   |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling;                |
+|           |            | serial port-interrupt               |
++-----------+------------+-------------------------------------+
+| WDT       | on-chip    | watchdog                            |
++-----------+------------+-------------------------------------+
+
+Other hardware features are not currently supported by Zephyr (at the moment)
+
+The default configuration can be found in the defconfig file:
+``boards/arm/npcx9m6f_evb/npcx9m6f_evb_defconfig``
+
+
+Connections and IOs
+===================
+
+Nuvoton to provide the schematic for this board.
+
+System Clock
+============
+
+The NPCX9M6F MCU is configured to use the 90Mhz internal oscillator with the
+on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock
+control register (chapter 4 in user manual)
+
+Serial Port
+===========
+
+UART1 is configured for serial logs.
+
+
+Programming and Debugging
+*************************
+
+This board comes with a Cortex ETM port which facilitates tracing and debugging
+using a single physical connection. In addition, it comes with sockets for
+JTAG-only sessions.
+
+Flashing
+========
+
+Build application as usual for the ``npcx9m6f_evb`` board, and flash
+using Servo V2, μServo, or Servo V4 (CCD). See the
+`Chromium EC Flashing Documentation`_ for more information.
+
+
+Debugging
+=========
+
+Use JTAG/SWD with a J-Link
+
+References
+**********
+.. target-notes::
+
+.. _Chromium EC Flashing Documentation:
+   https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board

boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts

@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nuvoton/npcx9m6f.dtsi>
+
+/ {
+	model = "Nuvoton NPCX9M6F evaluation board";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,flash = &flash0;
+	};
+
+	aliases {
+		/* For samples/basic/blinky_pwm */
+		pwm-led0 = &pwm_led0_green;
+		/* For gpio test suites */
+		led0 = &gpio_led_red;
+		/* For pwm test suites */
+		pwm-0 = &pwm6;
+		/* For i2c test suites */
+		i2c-0 = &i2c0_0;
+		/* For watchdog sample */
+		watchdog0 = &twd0;
+	};
+
+	leds-pwm {
+		compatible = "pwm-leds";
+		pwm_led0_green: pwm_led_0 {
+			pwms = <&pwm6 0 PWM_POLARITY_INVERTED>;
+			label = "User D7 green";
+		};
+	};
+
+	leds-gpio {
+		compatible = "gpio-leds";
+		gpio_led_red: led_0 {
+			gpios = <&gpio6 0 GPIO_ACTIVE_LOW>;
+			label = "User D8 red";
+		};
+	};
+
+	power-states {
+		suspend_to_idle0: suspend-to-idle0 {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-idle";
+			substate-id = <0>;
+			min-residency-us = <1000>;
+		};
+
+		suspend_to_idle1: suspend-to-idle1 {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-idle";
+			substate-id = <1>;
+			min-residency-us = <201000>;
+		};
+	};
+
+	vsby-psl-in-list {
+		psl-in-pads = <&psl_in1>; /* Use PSL_IN1 as detection pins */
+	};
+};
+
+&cpu0 {
+	cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>;
+};
+
+&psl_in1 {
+	/* A falling edge detection type for PSL_IN1 */
+	flag = <NPCX_PSL_FALLING_EDGE>;
+};
+
+/* Overwirte default device properties with overlays in board dt file here. */
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	/* Use UART1_SL2 ie. PIN64.65 */
+	pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>;
+};
+
+&pwm6 {
+	drive-open-drain;
+	status = "okay";
+};
+
+&adc0 {
+	/* ADC pinmux is changed only if related channel is configured. */
+	status = "okay";
+};
+
+&espi0 {
+	status = "okay";
+};
+
+&i2c0_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&tach1 {
+	status = "okay";
+	pinctrl-0 = <&alt3_ta1_sl1>; /* Use TA1_SL1 (PIN40) as input pin */
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <1>; /* number of pulses per round of encoder */
+};

boards/arm/npcx9m6f_evb/npcx9m6f_evb.yaml

@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: npcx9m6f_evb
+name: Nuvoton NPCX9M6F EVB
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 64
+flash: 256
+supported:
+  - adc
+  - clock
+  - gpio
+  - i2c
+  - pinmux
+  - pm
+  - pwm
+  - psl
+  - tach
+  - uart
+  - watchdog

boards/arm/npcx9m6f_evb/npcx9m6f_evb_defconfig

@@ -0,0 +1,59 @@
+#
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_SOC_NPCX9M6F=y
+CONFIG_SOC_SERIES_NPCX9=y
+CONFIG_BOARD_NPCX9M6F_EVB=y
+
+# Enable NPCX firmware header
+CONFIG_NPCX_HEADER=y
+CONFIG_NPCX_HEADER_SPI_MAX_CLOCK_50=y
+CONFIG_NPCX_HEADER_SPI_READ_MODE_DUAL=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# PLL configuration
+CONFIG_CLOCK_NPCX_OSC_CYCLES_PER_SEC=90000000
+CONFIG_CLOCK_NPCX_APB1_PRESCALER=6
+CONFIG_CLOCK_NPCX_APB2_PRESCALER=6
+CONFIG_CLOCK_NPCX_APB3_PRESCALER=6
+CONFIG_CLOCK_NPCX_APB4_PRESCALER=6
+
+# General Kernel Options
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000
+
+# UART Driver
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# GPIO Driver
+CONFIG_GPIO=y
+
+# PWM Driver
+CONFIG_PWM=y
+
+# ADC Driver
+CONFIG_ADC=y
+
+# WDT Driver
+CONFIG_WATCHDOG=y
+
+# ESPI Driver
+CONFIG_ESPI=y
+
+# I2C Driver
+CONFIG_I2C=y
+
+# Console Driver
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Power Management
+#CONFIG_SOC_POWER_MANAGEMENT=y

boards/arm/npcx9m6f_evb/support/openocd.cfg

@@ -0,0 +1,4 @@
+# script for Nuvoton NPCX Cortex-M4 Series
+
+source [find interface/jlink.cfg]
+source [find target/npcx.cfg]

tests/drivers/adc/adc_api/src/test_adc.c

@@ -261,7 +261,8 @@
 #define ADC_1ST_CHANNEL_ID	0
 #define ADC_2ND_CHANNEL_ID	1
 
-#elif defined(CONFIG_BOARD_NPCX7M6FB_EVB)
+#elif defined(CONFIG_BOARD_NPCX7M6FB_EVB) || \
+	defined(CONFIG_BOARD_NPCX9M6F_EVB)
 #define ADC_DEVICE_NAME		DT_LABEL(DT_INST(0, nuvoton_npcx_adc))
 #define ADC_RESOLUTION		10
 #define ADC_GAIN		ADC_GAIN_1

tests/drivers/gpio/gpio_basic_api/boards/npcx9m6f_evb.overlay

@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test,gpio_basic_api";
+		out-gpios = <&gpioc 5 0>; /* GPIO header 2 */
+		in-gpios = <&gpioc 6 0>;  /* GPIO header 3 */
+	};
+};