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soc: riscv32: Move rv32m1 sram memory definitions to dts

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Moves the sram memory definitions from Kconfig to device tree for the
rv32m1 ri5cy and zero-riscy cores.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm 2019-05-06 12:50:48 -05:00 • committed by Anas Nashif
commit cf1be5a3c5
6 changed files with 14 additions and 17 deletions
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2
boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts
View file

@ -13,7 +13,7 @@
compatible = "openisa,rv32m1"; compatible = "openisa,rv32m1";
chosen { chosen {
zephyr,sram = &sram0; zephyr,sram = &m4_dtcm;
zephyr,console = &uart0; zephyr,console = &uart0;
zephyr,uart-pipe = &uart0; zephyr,uart-pipe = &uart0;
}; };

2
boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy.dts
View file

@ -13,7 +13,7 @@
compatible = "openisa,rv32m1"; compatible = "openisa,rv32m1";
chosen { chosen {
zephyr,sram = &sram0; zephyr,sram = &m0_tcm;
zephyr,console = &uart0; zephyr,console = &uart0;
zephyr,uart-pipe = &uart0; zephyr,uart-pipe = &uart0;
}; };

8
dts/riscv32/rv32m1.dtsi
View file

@ -50,12 +50,18 @@
}; };
}; };
sram0: memory@20000000 { m4_dtcm: memory@20000000 {
device_type = "memory"; device_type = "memory";
compatible = "mmio-sram"; compatible = "mmio-sram";
reg = <0x20000000 0x30000>; reg = <0x20000000 0x30000>;
}; };
m0_tcm: memory@9000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x09000000 0x20000>;
};
soc { soc {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;

10
soc/riscv32/openisa_rv32m1/Kconfig.defconfig
View file

@ -62,16 +62,6 @@ config RISCV32_RV32M1_ROM_SIZE
default 0x000FFF00 if SOC_OPENISA_RV32M1_RI5CY default 0x000FFF00 if SOC_OPENISA_RV32M1_RI5CY
default 0x0003FF00 if SOC_OPENISA_RV32M1_ZERO_RISCY default 0x0003FF00 if SOC_OPENISA_RV32M1_ZERO_RISCY
config RISCV32_RV32M1_RAM_BASE_ADDR
hex
default 0x20000000 if SOC_OPENISA_RV32M1_RI5CY
default 0x09000000 if SOC_OPENISA_RV32M1_ZERO_RISCY
config RISCV32_RV32M1_RAM_SIZE
hex
default 0x00030000 if SOC_OPENISA_RV32M1_RI5CY
default 0x00020000 if SOC_OPENISA_RV32M1_ZERO_RISCY
# The event unit looks for vector tables at the end of each core's # The event unit looks for vector tables at the end of each core's
# flash space. These vector tables are not relocatable. # flash space. These vector tables are not relocatable.
config RISCV32_RV32M1_VECTOR_BASE_ADDR config RISCV32_RV32M1_VECTOR_BASE_ADDR

5
soc/riscv32/openisa_rv32m1/linker.ld
View file

@ -15,6 +15,7 @@
#define _LINKER #define _LINKER
#define _ASMLANGUAGE #define _ASMLANGUAGE
#include <generated_dts_board.h>
#include <autoconf.h> #include <autoconf.h>
#include <linker/sections.h> #include <linker/sections.h>
@ -30,8 +31,8 @@
#define ROM_BASE CONFIG_RISCV32_RV32M1_ROM_BASE_ADDR #define ROM_BASE CONFIG_RISCV32_RV32M1_ROM_BASE_ADDR
#define ROM_SIZE CONFIG_RISCV32_RV32M1_ROM_SIZE #define ROM_SIZE CONFIG_RISCV32_RV32M1_ROM_SIZE
#define RAM_BASE CONFIG_RISCV32_RV32M1_RAM_BASE_ADDR #define RAM_BASE DT_SRAM_BASE_ADDRESS
#define RAM_SIZE CONFIG_RISCV32_RV32M1_RAM_SIZE #define RAM_SIZE KB(DT_SRAM_SIZE)
#define VECTOR_BASE CONFIG_RISCV32_RV32M1_VECTOR_BASE_ADDR #define VECTOR_BASE CONFIG_RISCV32_RV32M1_VECTOR_BASE_ADDR
#define VECTOR_SIZE CONFIG_RISCV32_RV32M1_VECTOR_SIZE #define VECTOR_SIZE CONFIG_RISCV32_RV32M1_VECTOR_SIZE

4
soc/riscv32/openisa_rv32m1/soc.h
View file

@ -105,7 +105,7 @@ void soc_interrupt_init(void);
#endif #endif
/* Newlib hooks (and potentially other things) use these defines. */ /* Newlib hooks (and potentially other things) use these defines. */
#define RISCV_RAM_SIZE CONFIG_RISCV32_RV32M1_RAM_SIZE #define RISCV_RAM_SIZE KB(DT_SRAM_SIZE)
#define RISCV_RAM_BASE CONFIG_RISCV32_RV32M1_RAM_BASE_ADDR #define RISCV_RAM_BASE DT_SRAM_BASE_ADDRESS
#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_H_ */ #endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_H_ */