From cf1be5a3c5712c93b862baa2b57be7be93afa615 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Mon, 6 May 2019 12:50:48 -0500 Subject: [PATCH] soc: riscv32: Move rv32m1 sram memory definitions to dts Moves the sram memory definitions from Kconfig to device tree for the rv32m1 ri5cy and zero-riscy cores. Signed-off-by: Maureen Helm --- boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts | 2 +- boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy.dts | 2 +- dts/riscv32/rv32m1.dtsi | 8 +++++++- soc/riscv32/openisa_rv32m1/Kconfig.defconfig | 10 ---------- soc/riscv32/openisa_rv32m1/linker.ld | 5 +++-- soc/riscv32/openisa_rv32m1/soc.h | 4 ++-- 6 files changed, 14 insertions(+), 17 deletions(-) diff --git a/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts b/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts index 3e931994617..7fca5c83808 100644 --- a/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts +++ b/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts @@ -13,7 +13,7 @@ compatible = "openisa,rv32m1"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &m4_dtcm; zephyr,console = &uart0; zephyr,uart-pipe = &uart0; }; diff --git a/boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy.dts b/boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy.dts index c86fc58eb33..bcc6296ed7b 100644 --- a/boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy.dts +++ b/boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy.dts @@ -13,7 +13,7 @@ compatible = "openisa,rv32m1"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &m0_tcm; zephyr,console = &uart0; zephyr,uart-pipe = &uart0; }; diff --git a/dts/riscv32/rv32m1.dtsi b/dts/riscv32/rv32m1.dtsi index 0a4e10b39d4..db65a2abbfc 100644 --- a/dts/riscv32/rv32m1.dtsi +++ b/dts/riscv32/rv32m1.dtsi @@ -50,12 +50,18 @@ }; }; - sram0: memory@20000000 { + m4_dtcm: memory@20000000 { device_type = "memory"; compatible = "mmio-sram"; reg = <0x20000000 0x30000>; }; + m0_tcm: memory@9000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x09000000 0x20000>; + }; + soc { #address-cells = <1>; #size-cells = <1>; diff --git a/soc/riscv32/openisa_rv32m1/Kconfig.defconfig b/soc/riscv32/openisa_rv32m1/Kconfig.defconfig index 8d85e97b2c4..90fc4532636 100644 --- a/soc/riscv32/openisa_rv32m1/Kconfig.defconfig +++ b/soc/riscv32/openisa_rv32m1/Kconfig.defconfig @@ -62,16 +62,6 @@ config RISCV32_RV32M1_ROM_SIZE default 0x000FFF00 if SOC_OPENISA_RV32M1_RI5CY default 0x0003FF00 if SOC_OPENISA_RV32M1_ZERO_RISCY -config RISCV32_RV32M1_RAM_BASE_ADDR - hex - default 0x20000000 if SOC_OPENISA_RV32M1_RI5CY - default 0x09000000 if SOC_OPENISA_RV32M1_ZERO_RISCY - -config RISCV32_RV32M1_RAM_SIZE - hex - default 0x00030000 if SOC_OPENISA_RV32M1_RI5CY - default 0x00020000 if SOC_OPENISA_RV32M1_ZERO_RISCY - # The event unit looks for vector tables at the end of each core's # flash space. These vector tables are not relocatable. config RISCV32_RV32M1_VECTOR_BASE_ADDR diff --git a/soc/riscv32/openisa_rv32m1/linker.ld b/soc/riscv32/openisa_rv32m1/linker.ld index b98d0241618..204ac1051f8 100644 --- a/soc/riscv32/openisa_rv32m1/linker.ld +++ b/soc/riscv32/openisa_rv32m1/linker.ld @@ -15,6 +15,7 @@ #define _LINKER #define _ASMLANGUAGE +#include #include #include @@ -30,8 +31,8 @@ #define ROM_BASE CONFIG_RISCV32_RV32M1_ROM_BASE_ADDR #define ROM_SIZE CONFIG_RISCV32_RV32M1_ROM_SIZE -#define RAM_BASE CONFIG_RISCV32_RV32M1_RAM_BASE_ADDR -#define RAM_SIZE CONFIG_RISCV32_RV32M1_RAM_SIZE +#define RAM_BASE DT_SRAM_BASE_ADDRESS +#define RAM_SIZE KB(DT_SRAM_SIZE) #define VECTOR_BASE CONFIG_RISCV32_RV32M1_VECTOR_BASE_ADDR #define VECTOR_SIZE CONFIG_RISCV32_RV32M1_VECTOR_SIZE diff --git a/soc/riscv32/openisa_rv32m1/soc.h b/soc/riscv32/openisa_rv32m1/soc.h index bb9f803e47d..50b9023add6 100644 --- a/soc/riscv32/openisa_rv32m1/soc.h +++ b/soc/riscv32/openisa_rv32m1/soc.h @@ -105,7 +105,7 @@ void soc_interrupt_init(void); #endif /* Newlib hooks (and potentially other things) use these defines. */ -#define RISCV_RAM_SIZE CONFIG_RISCV32_RV32M1_RAM_SIZE -#define RISCV_RAM_BASE CONFIG_RISCV32_RV32M1_RAM_BASE_ADDR +#define RISCV_RAM_SIZE KB(DT_SRAM_SIZE) +#define RISCV_RAM_BASE DT_SRAM_BASE_ADDRESS #endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_H_ */