xtensa: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same level as boards and architectures allowing both SoCs and boards to be maintained outside the tree. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif
parent
f183444682
commit
cea0b3a9c2
58 changed files with 9 additions and 17 deletions
1
soc/xtensa/sample_controller/CMakeLists.txt
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1
soc/xtensa/sample_controller/CMakeLists.txt
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@ -0,0 +1 @@
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# intentionally left empty
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19
soc/xtensa/sample_controller/Kconfig.defconfig
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19
soc/xtensa/sample_controller/Kconfig.defconfig
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@ -0,0 +1,19 @@
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# Kconfig - XTENSA board configuration
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#
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# Copyright (c) 2016 Open-RnD Sp. z o.o.
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_XTENSA_SAMPLE_CONTROLLER
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config SOC
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string
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default "sample_controller"
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config IRQ_OFFLOAD_INTNUM
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default 7
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config XTENSA_ASM2
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def_bool y
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endif
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6
soc/xtensa/sample_controller/Kconfig.soc
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6
soc/xtensa/sample_controller/Kconfig.soc
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@ -0,0 +1,6 @@
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_XTENSA_SAMPLE_CONTROLLER
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bool "Xtensa sample_controller core"
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272
soc/xtensa/sample_controller/include/_soc_inthandlers.h
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272
soc/xtensa/sample_controller/include/_soc_inthandlers.h
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@ -0,0 +1,272 @@
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/*
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* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
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*
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* Functions here are designed to produce efficient code to
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* search an Xtensa bitmask of interrupts, inspecting only those bits
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* declared to be associated with a given interrupt level. Each
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* dispatcher will handle exactly one flagged interrupt, in numerical
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* order (low bits first) and will return a mask of that bit that can
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* then be cleared by the calling code. Unrecognized bits for the
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* level will invoke an error handler.
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*/
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#include <xtensa/config/core-isa.h>
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#include <sw_isr_table.h>
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#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 4
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 5
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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static inline int _xtensa_handle_one_int0(unsigned int mask)
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{
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return 0;
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}
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static inline int _xtensa_handle_one_int1(unsigned int mask)
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{
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if (mask & 0x7f) {
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if (mask & 0x7) {
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if (mask & (1 << 0)) {
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struct _isr_table_entry *e = &_sw_isr_table[0];
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e->isr(e->arg);
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return 1 << 0;
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}
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if (mask & (1 << 1)) {
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struct _isr_table_entry *e = &_sw_isr_table[1];
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e->isr(e->arg);
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return 1 << 1;
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}
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if (mask & (1 << 2)) {
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struct _isr_table_entry *e = &_sw_isr_table[2];
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e->isr(e->arg);
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return 1 << 2;
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}
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} else {
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if (mask & 0x18) {
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if (mask & (1 << 3)) {
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struct _isr_table_entry *e = &_sw_isr_table[3];
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e->isr(e->arg);
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return 1 << 3;
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}
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if (mask & (1 << 4)) {
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struct _isr_table_entry *e = &_sw_isr_table[4];
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e->isr(e->arg);
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return 1 << 4;
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}
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} else {
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if (mask & (1 << 5)) {
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struct _isr_table_entry *e = &_sw_isr_table[5];
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e->isr(e->arg);
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return 1 << 5;
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}
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if (mask & (1 << 6)) {
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struct _isr_table_entry *e = &_sw_isr_table[6];
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e->isr(e->arg);
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return 1 << 6;
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}
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}
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}
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} else {
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if (mask & 0x18080) {
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if (mask & (1 << 7)) {
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struct _isr_table_entry *e = &_sw_isr_table[7];
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e->isr(e->arg);
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return 1 << 7;
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}
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if (mask & (1 << 15)) {
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struct _isr_table_entry *e = &_sw_isr_table[15];
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e->isr(e->arg);
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return 1 << 15;
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}
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if (mask & (1 << 16)) {
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struct _isr_table_entry *e = &_sw_isr_table[16];
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e->isr(e->arg);
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return 1 << 16;
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}
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} else {
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if (mask & 0x60000) {
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if (mask & (1 << 17)) {
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struct _isr_table_entry *e = &_sw_isr_table[17];
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e->isr(e->arg);
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return 1 << 17;
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}
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if (mask & (1 << 18)) {
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struct _isr_table_entry *e = &_sw_isr_table[18];
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e->isr(e->arg);
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return 1 << 18;
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}
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} else {
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if (mask & (1 << 19)) {
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struct _isr_table_entry *e = &_sw_isr_table[19];
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e->isr(e->arg);
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return 1 << 19;
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}
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if (mask & (1 << 20)) {
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struct _isr_table_entry *e = &_sw_isr_table[20];
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e->isr(e->arg);
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return 1 << 20;
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}
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}
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}
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}
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return 0;
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}
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static inline int _xtensa_handle_one_int2(unsigned int mask)
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{
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if (mask & (1 << 8)) {
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struct _isr_table_entry *e = &_sw_isr_table[8];
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e->isr(e->arg);
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return 1 << 8;
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}
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return 0;
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}
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static inline int _xtensa_handle_one_int3(unsigned int mask)
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{
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if (mask & 0x600) {
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if (mask & (1 << 9)) {
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struct _isr_table_entry *e = &_sw_isr_table[9];
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e->isr(e->arg);
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return 1 << 9;
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}
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if (mask & (1 << 10)) {
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struct _isr_table_entry *e = &_sw_isr_table[10];
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e->isr(e->arg);
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return 1 << 10;
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}
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} else {
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if (mask & (1 << 11)) {
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struct _isr_table_entry *e = &_sw_isr_table[11];
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e->isr(e->arg);
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return 1 << 11;
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}
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if (mask & (1 << 21)) {
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struct _isr_table_entry *e = &_sw_isr_table[21];
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e->isr(e->arg);
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return 1 << 21;
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}
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}
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return 0;
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}
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static inline int _xtensa_handle_one_int4(unsigned int mask)
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{
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if (mask & (1 << 12)) {
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struct _isr_table_entry *e = &_sw_isr_table[12];
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e->isr(e->arg);
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return 1 << 12;
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}
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return 0;
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}
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static inline int _xtensa_handle_one_int5(unsigned int mask)
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{
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if (mask & (1 << 13)) {
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struct _isr_table_entry *e = &_sw_isr_table[13];
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e->isr(e->arg);
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return 1 << 13;
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}
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return 0;
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}
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static inline int _xtensa_handle_one_int6(unsigned int mask)
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{
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return 0;
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}
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static inline int _xtensa_handle_one_int7(unsigned int mask)
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{
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if (mask & (1 << 14)) {
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struct _isr_table_entry *e = &_sw_isr_table[14];
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e->isr(e->arg);
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return 1 << 14;
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}
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return 0;
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}
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607
soc/xtensa/sample_controller/linker.ld
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607
soc/xtensa/sample_controller/linker.ld
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/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* Linker script for the Xtensa platform.
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*/
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#define _LINKER
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#define _ASMLANGUAGE
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#include <autoconf.h>
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#include <linker/sections.h>
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#include <linker/linker-defs.h>
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#include <linker/linker-tool.h>
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#define RAMABLE_REGION sram0_seg :sram0_phdr
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#define ROMABLE_REGION srom1_seg :srom1_phdr
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MEMORY
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{
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dram1_0_seg : org = 0x3FFC0000, len = 0x20000
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dram0_0_seg : org = 0x3FFE0000, len = 0x20000
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iram0_0_seg : org = 0x40000000, len = 0x178
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iram0_1_seg : org = 0x40000178, len = 0x8
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iram0_2_seg : org = 0x40000180, len = 0x38
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iram0_3_seg : org = 0x400001B8, len = 0x8
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iram0_4_seg : org = 0x400001C0, len = 0x38
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iram0_5_seg : org = 0x400001F8, len = 0x8
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iram0_6_seg : org = 0x40000200, len = 0x38
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iram0_7_seg : org = 0x40000238, len = 0x8
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iram0_8_seg : org = 0x40000240, len = 0x38
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iram0_9_seg : org = 0x40000278, len = 0x8
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iram0_10_seg : org = 0x40000280, len = 0x38
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iram0_11_seg : org = 0x400002B8, len = 0x8
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iram0_12_seg : org = 0x400002C0, len = 0x38
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iram0_13_seg : org = 0x400002F8, len = 0x8
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iram0_14_seg : org = 0x40000300, len = 0x38
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iram0_15_seg : org = 0x40000338, len = 0x8
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iram0_16_seg : org = 0x40000340, len = 0x38
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iram0_17_seg : org = 0x40000378, len = 0x48
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iram0_18_seg : org = 0x400003C0, len = 0x40
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iram0_19_seg : org = 0x40000400, len = 0x1FC00
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srom0_seg : org = 0x50000000, len = 0x300
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srom1_seg : org = 0x50000300, len = 0xFFFD00
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sram0_seg : org = 0x60000000, len = 0x4000000
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0x3ffbe000, len = 0x2000
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#endif
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}
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PHDRS
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{
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dram1_0_phdr PT_LOAD;
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dram1_0_bss_phdr PT_LOAD;
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dram0_0_phdr PT_LOAD;
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dram0_0_bss_phdr PT_LOAD;
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iram0_0_phdr PT_LOAD;
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iram0_1_phdr PT_LOAD;
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iram0_2_phdr PT_LOAD;
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iram0_3_phdr PT_LOAD;
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iram0_4_phdr PT_LOAD;
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iram0_5_phdr PT_LOAD;
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iram0_6_phdr PT_LOAD;
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iram0_7_phdr PT_LOAD;
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iram0_8_phdr PT_LOAD;
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iram0_9_phdr PT_LOAD;
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iram0_10_phdr PT_LOAD;
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iram0_11_phdr PT_LOAD;
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iram0_12_phdr PT_LOAD;
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iram0_13_phdr PT_LOAD;
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iram0_14_phdr PT_LOAD;
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iram0_15_phdr PT_LOAD;
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iram0_16_phdr PT_LOAD;
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iram0_17_phdr PT_LOAD;
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iram0_18_phdr PT_LOAD;
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iram0_19_phdr PT_LOAD;
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srom0_phdr PT_LOAD;
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srom1_phdr PT_LOAD;
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sram0_phdr PT_LOAD;
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sram0_bss_phdr PT_LOAD;
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}
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/* Default entry point: */
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ENTRY(CONFIG_KERNEL_ENTRY)
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/* Memory boundary addresses: */
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_memmap_mem_dram1_start = 0x3ffc0000;
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_memmap_mem_dram1_end = 0x3ffe0000;
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_memmap_mem_dram0_start = 0x3ffe0000;
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_memmap_mem_dram0_end = 0x40000000;
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_memmap_mem_iram0_start = 0x40000000;
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_memmap_mem_iram0_end = 0x40020000;
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_memmap_mem_srom_start = 0x50000000;
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_memmap_mem_srom_end = 0x51000000;
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_memmap_mem_sram_start = 0x60000000;
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_memmap_mem_sram_end = 0x64000000;
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/* Memory segment boundary addresses: */
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_memmap_seg_dram1_0_start = 0x3ffc0000;
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_memmap_seg_dram1_0_max = 0x3ffe0000;
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_memmap_seg_dram0_0_start = 0x3ffe0000;
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_memmap_seg_dram0_0_max = 0x40000000;
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_memmap_seg_iram0_0_start = 0x40000000;
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_memmap_seg_iram0_0_max = 0x40000178;
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_memmap_seg_iram0_1_start = 0x40000178;
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_memmap_seg_iram0_1_max = 0x40000180;
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_memmap_seg_iram0_2_start = 0x40000180;
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_memmap_seg_iram0_2_max = 0x400001b8;
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_memmap_seg_iram0_3_start = 0x400001b8;
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_memmap_seg_iram0_3_max = 0x400001c0;
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_memmap_seg_iram0_4_start = 0x400001c0;
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_memmap_seg_iram0_4_max = 0x400001f8;
|
||||
_memmap_seg_iram0_5_start = 0x400001f8;
|
||||
_memmap_seg_iram0_5_max = 0x40000200;
|
||||
_memmap_seg_iram0_6_start = 0x40000200;
|
||||
_memmap_seg_iram0_6_max = 0x40000238;
|
||||
_memmap_seg_iram0_7_start = 0x40000238;
|
||||
_memmap_seg_iram0_7_max = 0x40000240;
|
||||
_memmap_seg_iram0_8_start = 0x40000240;
|
||||
_memmap_seg_iram0_8_max = 0x40000278;
|
||||
_memmap_seg_iram0_9_start = 0x40000278;
|
||||
_memmap_seg_iram0_9_max = 0x40000280;
|
||||
_memmap_seg_iram0_10_start = 0x40000280;
|
||||
_memmap_seg_iram0_10_max = 0x400002b8;
|
||||
_memmap_seg_iram0_11_start = 0x400002b8;
|
||||
_memmap_seg_iram0_11_max = 0x400002c0;
|
||||
_memmap_seg_iram0_12_start = 0x400002c0;
|
||||
_memmap_seg_iram0_12_max = 0x400002f8;
|
||||
_memmap_seg_iram0_13_start = 0x400002f8;
|
||||
_memmap_seg_iram0_13_max = 0x40000300;
|
||||
_memmap_seg_iram0_14_start = 0x40000300;
|
||||
_memmap_seg_iram0_14_max = 0x40000338;
|
||||
_memmap_seg_iram0_15_start = 0x40000338;
|
||||
_memmap_seg_iram0_15_max = 0x40000340;
|
||||
_memmap_seg_iram0_16_start = 0x40000340;
|
||||
_memmap_seg_iram0_16_max = 0x40000378;
|
||||
_memmap_seg_iram0_17_start = 0x40000378;
|
||||
_memmap_seg_iram0_17_max = 0x400003c0;
|
||||
_memmap_seg_iram0_18_start = 0x400003c0;
|
||||
_memmap_seg_iram0_18_max = 0x40000400;
|
||||
_memmap_seg_iram0_19_start = 0x40000400;
|
||||
_memmap_seg_iram0_19_max = 0x40020000;
|
||||
_memmap_seg_srom0_start = 0x50000000;
|
||||
_memmap_seg_srom0_max = 0x50000300;
|
||||
_memmap_seg_srom1_start = 0x50000300;
|
||||
_memmap_seg_srom1_max = 0x51000000;
|
||||
_memmap_seg_sram0_start = 0x60000000;
|
||||
_memmap_seg_sram0_max = 0x64000000;
|
||||
|
||||
_rom_store_table = 0;
|
||||
PROVIDE(_memmap_vecbase_reset = 0x40000000);
|
||||
PROVIDE(_memmap_reset_vector = 0x50000000);
|
||||
/* Various memory-map dependent cache attribute settings: */
|
||||
_memmap_cacheattr_wb_base = 0x00001110;
|
||||
_memmap_cacheattr_wt_base = 0x00001110;
|
||||
_memmap_cacheattr_bp_base = 0x00002220;
|
||||
_memmap_cacheattr_unused_mask = 0xFFFF000F;
|
||||
_memmap_cacheattr_wb_trapnull = 0x2222111F;
|
||||
_memmap_cacheattr_wba_trapnull = 0x2222111F;
|
||||
_memmap_cacheattr_wbna_trapnull = 0x2222111F;
|
||||
_memmap_cacheattr_wt_trapnull = 0x2222111F;
|
||||
_memmap_cacheattr_bp_trapnull = 0x2222222F;
|
||||
_memmap_cacheattr_wb_strict = 0xFFFF111F;
|
||||
_memmap_cacheattr_wt_strict = 0xFFFF111F;
|
||||
_memmap_cacheattr_bp_strict = 0xFFFF222F;
|
||||
_memmap_cacheattr_wb_allvalid = 0x22221112;
|
||||
_memmap_cacheattr_wt_allvalid = 0x22221112;
|
||||
_memmap_cacheattr_bp_allvalid = 0x22222222;
|
||||
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
.dram1.rodata : ALIGN(4)
|
||||
{
|
||||
_dram1_rodata_start = ABSOLUTE(.);
|
||||
*(.dram1.rodata)
|
||||
_dram1_rodata_end = ABSOLUTE(.);
|
||||
} >dram1_0_seg :dram1_0_phdr
|
||||
|
||||
.dram1.literal : ALIGN(4)
|
||||
{
|
||||
_dram1_literal_start = ABSOLUTE(.);
|
||||
*(.dram1.literal)
|
||||
_dram1_literal_end = ABSOLUTE(.);
|
||||
} >dram1_0_seg :dram1_0_phdr
|
||||
|
||||
.dram1.data : ALIGN(4)
|
||||
{
|
||||
_dram1_data_start = ABSOLUTE(.);
|
||||
*(.dram1.data)
|
||||
_dram1_data_end = ABSOLUTE(.);
|
||||
} >dram1_0_seg :dram1_0_phdr
|
||||
|
||||
.dram1.bss (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_dram1_bss_start = ABSOLUTE(.);
|
||||
*(.dram1.bss)
|
||||
. = ALIGN (8);
|
||||
_dram1_bss_end = ABSOLUTE(.);
|
||||
_memmap_seg_dram1_0_end = ALIGN(0x8);
|
||||
} >dram1_0_seg :dram1_0_bss_phdr
|
||||
|
||||
.dram0.rodata : ALIGN(4)
|
||||
{
|
||||
_dram0_rodata_start = ABSOLUTE(.);
|
||||
*(.dram0.rodata)
|
||||
_dram0_rodata_end = ABSOLUTE(.);
|
||||
} >dram0_0_seg :dram0_0_phdr
|
||||
|
||||
.dram0.literal : ALIGN(4)
|
||||
{
|
||||
_dram0_literal_start = ABSOLUTE(.);
|
||||
*(.dram0.literal)
|
||||
_dram0_literal_end = ABSOLUTE(.);
|
||||
} >dram0_0_seg :dram0_0_phdr
|
||||
|
||||
.dram0.data : ALIGN(4)
|
||||
{
|
||||
_dram0_data_start = ABSOLUTE(.);
|
||||
*(.dram0.data)
|
||||
_dram0_data_end = ABSOLUTE(.);
|
||||
} >dram0_0_seg :dram0_0_phdr
|
||||
|
||||
.dram0.bss (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_dram0_bss_start = ABSOLUTE(.);
|
||||
*(.dram0.bss)
|
||||
. = ALIGN (8);
|
||||
_dram0_bss_end = ABSOLUTE(.);
|
||||
_memmap_seg_dram0_0_end = ALIGN(0x8);
|
||||
} >dram0_0_seg :dram0_0_bss_phdr
|
||||
|
||||
.WindowVectors.text : ALIGN(4)
|
||||
{
|
||||
_WindowVectors_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.WindowVectors.text))
|
||||
_WindowVectors_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_0_end = ALIGN(0x8);
|
||||
} >iram0_0_seg :iram0_0_phdr
|
||||
|
||||
.Level2InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level2InterruptVector.literal)
|
||||
_Level2InterruptVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_1_end = ALIGN(0x8);
|
||||
} >iram0_1_seg :iram0_1_phdr
|
||||
|
||||
.Level2InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level2InterruptVector.text))
|
||||
_Level2InterruptVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_2_end = ALIGN(0x8);
|
||||
} >iram0_2_seg :iram0_2_phdr
|
||||
|
||||
.Level3InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level3InterruptVector.literal)
|
||||
_Level3InterruptVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_3_end = ALIGN(0x8);
|
||||
} >iram0_3_seg :iram0_3_phdr
|
||||
|
||||
.Level3InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level3InterruptVector.text))
|
||||
_Level3InterruptVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_4_end = ALIGN(0x8);
|
||||
} >iram0_4_seg :iram0_4_phdr
|
||||
|
||||
.Level4InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level4InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level4InterruptVector.literal)
|
||||
_Level4InterruptVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_5_end = ALIGN(0x8);
|
||||
} >iram0_5_seg :iram0_5_phdr
|
||||
|
||||
.Level4InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level4InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level4InterruptVector.text))
|
||||
_Level4InterruptVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_6_end = ALIGN(0x8);
|
||||
} >iram0_6_seg :iram0_6_phdr
|
||||
|
||||
.Level5InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level5InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level5InterruptVector.literal)
|
||||
_Level5InterruptVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_7_end = ALIGN(0x8);
|
||||
} >iram0_7_seg :iram0_7_phdr
|
||||
|
||||
.Level5InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level5InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level5InterruptVector.text))
|
||||
_Level5InterruptVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_8_end = ALIGN(0x8);
|
||||
} >iram0_8_seg :iram0_8_phdr
|
||||
|
||||
.DebugExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DebugExceptionVector.literal)
|
||||
_DebugExceptionVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_9_end = ALIGN(0x8);
|
||||
} >iram0_9_seg :iram0_9_phdr
|
||||
|
||||
.DebugExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DebugExceptionVector.text))
|
||||
_DebugExceptionVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_10_end = ALIGN(0x8);
|
||||
} >iram0_10_seg :iram0_10_phdr
|
||||
|
||||
.NMIExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_NMIExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.NMIExceptionVector.literal)
|
||||
_NMIExceptionVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_11_end = ALIGN(0x8);
|
||||
} >iram0_11_seg :iram0_11_phdr
|
||||
|
||||
.NMIExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_NMIExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.NMIExceptionVector.text))
|
||||
_NMIExceptionVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_12_end = ALIGN(0x8);
|
||||
} >iram0_12_seg :iram0_12_phdr
|
||||
|
||||
.KernelExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.KernelExceptionVector.literal)
|
||||
_KernelExceptionVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_13_end = ALIGN(0x8);
|
||||
} >iram0_13_seg :iram0_13_phdr
|
||||
|
||||
.KernelExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.KernelExceptionVector.text))
|
||||
_KernelExceptionVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_14_end = ALIGN(0x8);
|
||||
} >iram0_14_seg :iram0_14_phdr
|
||||
|
||||
.UserExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.UserExceptionVector.literal)
|
||||
_UserExceptionVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_15_end = ALIGN(0x8);
|
||||
} >iram0_15_seg :iram0_15_phdr
|
||||
|
||||
.UserExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.UserExceptionVector.text))
|
||||
_UserExceptionVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_16_end = ALIGN(0x8);
|
||||
} >iram0_16_seg :iram0_16_phdr
|
||||
|
||||
.DoubleExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DoubleExceptionVector.literal)
|
||||
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_17_end = ALIGN(0x8);
|
||||
} >iram0_17_seg :iram0_17_phdr
|
||||
|
||||
.DoubleExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DoubleExceptionVector.text))
|
||||
_DoubleExceptionVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_18_end = ALIGN(0x8);
|
||||
} >iram0_18_seg :iram0_18_phdr
|
||||
|
||||
.iram0.text : ALIGN(4)
|
||||
{
|
||||
_iram0_text_start = ABSOLUTE(.);
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
_iram0_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_iram0_19_end = ALIGN(0x8);
|
||||
} >iram0_19_seg :iram0_19_phdr
|
||||
|
||||
.ResetVector.text : ALIGN(4)
|
||||
{
|
||||
_image_rom_start = ABSOLUTE(.);
|
||||
_ResetVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.ResetVector.text))
|
||||
_ResetVector_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom0_end = ALIGN(0x8);
|
||||
} >srom0_seg :srom0_phdr
|
||||
|
||||
.srom.rodata : ALIGN(4)
|
||||
{
|
||||
_srom_rodata_start = ABSOLUTE(.);
|
||||
*(.srom.rodata)
|
||||
_srom_rodata_end = ABSOLUTE(.);
|
||||
} >srom1_seg :srom1_phdr
|
||||
|
||||
.srom.text : ALIGN(4)
|
||||
{
|
||||
_srom_text_start = ABSOLUTE(.);
|
||||
*(.srom.literal .srom.text)
|
||||
_srom_text_end = ABSOLUTE(.);
|
||||
_memmap_seg_srom1_end = ALIGN(0x8);
|
||||
_image_rom_end = ABSOLUTE(.);
|
||||
} >srom1_seg :srom1_phdr
|
||||
|
||||
.sram.rodata : ALIGN(4)
|
||||
{
|
||||
_image_ram_start = ABSOLUTE(.);
|
||||
_sram_rodata_start = ABSOLUTE(.);
|
||||
*(.sram.rodata)
|
||||
_sram_rodata_end = ABSOLUTE(.);
|
||||
} >sram0_seg :sram0_phdr
|
||||
|
||||
#include <linker/common-rom.ld>
|
||||
|
||||
.rodata : ALIGN(4)
|
||||
{
|
||||
_rodata_start = ABSOLUTE(.);
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
|
||||
KEEP (*(.xt_except_table))
|
||||
KEEP (*(.gcc_except_table))
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
KEEP (*(.eh_frame))
|
||||
/* C++ constructor and destructor tables, properly ordered: */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4); /* this table MUST be 4-byte aligned */
|
||||
_bss_table_start = ABSOLUTE(.);
|
||||
LONG(_dram1_bss_start)
|
||||
LONG(_dram1_bss_end)
|
||||
LONG(_dram0_bss_start)
|
||||
LONG(_dram0_bss_end)
|
||||
LONG(_bss_start)
|
||||
LONG(_bss_end)
|
||||
_bss_table_end = ABSOLUTE(.);
|
||||
_rodata_end = ABSOLUTE(.);
|
||||
} >sram0_seg :sram0_phdr
|
||||
|
||||
.sram.text : ALIGN(4)
|
||||
{
|
||||
_sram_text_start = ABSOLUTE(.);
|
||||
*(.sram.literal .sram.text)
|
||||
_sram_text_end = ABSOLUTE(.);
|
||||
} >sram0_seg :sram0_phdr
|
||||
|
||||
_image_text_start = ALIGN(4);
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
KEEP(*(.init))
|
||||
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.fini.literal)
|
||||
KEEP(*(.fini))
|
||||
*(.gnu.version)
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
} >sram0_seg :sram0_phdr
|
||||
_image_text_end = .;
|
||||
|
||||
.sram.data : ALIGN(4)
|
||||
{
|
||||
_sram_data_start = ABSOLUTE(.);
|
||||
*(.sram.data)
|
||||
_sram_data_end = ABSOLUTE(.);
|
||||
} >sram0_seg :sram0_phdr
|
||||
|
||||
.noinit : ALIGN(4)
|
||||
{
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
} >sram0_seg :sram0_phdr
|
||||
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
_data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
KEEP(*(SW_ISR_TABLE))
|
||||
*(.gnu.linkonce.d.*)
|
||||
KEEP(*(.gnu.linkonce.d.*personality*))
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
KEEP(*(.jcr))
|
||||
_data_end = ABSOLUTE(.);
|
||||
} >sram0_seg :sram0_phdr
|
||||
|
||||
#include <linker/common-ram.ld>
|
||||
|
||||
.bss (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
*(.sram.bss)
|
||||
. = ALIGN (8);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
_end = ALIGN(0x8);
|
||||
_image_ram_end = ABSOLUTE(.);
|
||||
PROVIDE(end = ALIGN(0x8));
|
||||
_stack_sentry = ALIGN(0x8);
|
||||
_memmap_seg_sram0_end = ALIGN(0x8);
|
||||
} >sram0_seg :sram0_bss_phdr
|
||||
__stack = 0x64000000;
|
||||
_heap_sentry = 0x64000000;
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.debug.xt.callgraph 0 :
|
||||
{
|
||||
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
|
||||
}
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <linker/intlist.ld>
|
||||
#endif
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue