cea0b3a9c2
Move the SoC outside of the architecture tree and put them at the same level as boards and architectures allowing both SoCs and boards to be maintained outside the tree. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
607 lines
18 KiB
Text
607 lines
18 KiB
Text
/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* Linker script for the Xtensa platform.
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*/
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#define _LINKER
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#define _ASMLANGUAGE
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#include <autoconf.h>
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#include <linker/sections.h>
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#include <linker/linker-defs.h>
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#include <linker/linker-tool.h>
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#define RAMABLE_REGION sram0_seg :sram0_phdr
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#define ROMABLE_REGION srom1_seg :srom1_phdr
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MEMORY
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{
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dram1_0_seg : org = 0x3FFC0000, len = 0x20000
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dram0_0_seg : org = 0x3FFE0000, len = 0x20000
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iram0_0_seg : org = 0x40000000, len = 0x178
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iram0_1_seg : org = 0x40000178, len = 0x8
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iram0_2_seg : org = 0x40000180, len = 0x38
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iram0_3_seg : org = 0x400001B8, len = 0x8
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iram0_4_seg : org = 0x400001C0, len = 0x38
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iram0_5_seg : org = 0x400001F8, len = 0x8
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iram0_6_seg : org = 0x40000200, len = 0x38
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iram0_7_seg : org = 0x40000238, len = 0x8
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iram0_8_seg : org = 0x40000240, len = 0x38
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iram0_9_seg : org = 0x40000278, len = 0x8
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iram0_10_seg : org = 0x40000280, len = 0x38
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iram0_11_seg : org = 0x400002B8, len = 0x8
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iram0_12_seg : org = 0x400002C0, len = 0x38
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iram0_13_seg : org = 0x400002F8, len = 0x8
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iram0_14_seg : org = 0x40000300, len = 0x38
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iram0_15_seg : org = 0x40000338, len = 0x8
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iram0_16_seg : org = 0x40000340, len = 0x38
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iram0_17_seg : org = 0x40000378, len = 0x48
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iram0_18_seg : org = 0x400003C0, len = 0x40
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iram0_19_seg : org = 0x40000400, len = 0x1FC00
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srom0_seg : org = 0x50000000, len = 0x300
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srom1_seg : org = 0x50000300, len = 0xFFFD00
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sram0_seg : org = 0x60000000, len = 0x4000000
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0x3ffbe000, len = 0x2000
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#endif
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}
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PHDRS
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{
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dram1_0_phdr PT_LOAD;
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dram1_0_bss_phdr PT_LOAD;
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dram0_0_phdr PT_LOAD;
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dram0_0_bss_phdr PT_LOAD;
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iram0_0_phdr PT_LOAD;
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iram0_1_phdr PT_LOAD;
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iram0_2_phdr PT_LOAD;
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iram0_3_phdr PT_LOAD;
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iram0_4_phdr PT_LOAD;
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iram0_5_phdr PT_LOAD;
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iram0_6_phdr PT_LOAD;
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iram0_7_phdr PT_LOAD;
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iram0_8_phdr PT_LOAD;
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iram0_9_phdr PT_LOAD;
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iram0_10_phdr PT_LOAD;
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iram0_11_phdr PT_LOAD;
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iram0_12_phdr PT_LOAD;
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iram0_13_phdr PT_LOAD;
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iram0_14_phdr PT_LOAD;
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iram0_15_phdr PT_LOAD;
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iram0_16_phdr PT_LOAD;
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iram0_17_phdr PT_LOAD;
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iram0_18_phdr PT_LOAD;
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iram0_19_phdr PT_LOAD;
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srom0_phdr PT_LOAD;
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srom1_phdr PT_LOAD;
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sram0_phdr PT_LOAD;
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sram0_bss_phdr PT_LOAD;
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}
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/* Default entry point: */
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ENTRY(CONFIG_KERNEL_ENTRY)
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/* Memory boundary addresses: */
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_memmap_mem_dram1_start = 0x3ffc0000;
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_memmap_mem_dram1_end = 0x3ffe0000;
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_memmap_mem_dram0_start = 0x3ffe0000;
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_memmap_mem_dram0_end = 0x40000000;
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_memmap_mem_iram0_start = 0x40000000;
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_memmap_mem_iram0_end = 0x40020000;
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_memmap_mem_srom_start = 0x50000000;
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_memmap_mem_srom_end = 0x51000000;
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_memmap_mem_sram_start = 0x60000000;
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_memmap_mem_sram_end = 0x64000000;
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/* Memory segment boundary addresses: */
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_memmap_seg_dram1_0_start = 0x3ffc0000;
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_memmap_seg_dram1_0_max = 0x3ffe0000;
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_memmap_seg_dram0_0_start = 0x3ffe0000;
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_memmap_seg_dram0_0_max = 0x40000000;
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_memmap_seg_iram0_0_start = 0x40000000;
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_memmap_seg_iram0_0_max = 0x40000178;
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_memmap_seg_iram0_1_start = 0x40000178;
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_memmap_seg_iram0_1_max = 0x40000180;
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_memmap_seg_iram0_2_start = 0x40000180;
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_memmap_seg_iram0_2_max = 0x400001b8;
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_memmap_seg_iram0_3_start = 0x400001b8;
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_memmap_seg_iram0_3_max = 0x400001c0;
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_memmap_seg_iram0_4_start = 0x400001c0;
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_memmap_seg_iram0_4_max = 0x400001f8;
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_memmap_seg_iram0_5_start = 0x400001f8;
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_memmap_seg_iram0_5_max = 0x40000200;
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_memmap_seg_iram0_6_start = 0x40000200;
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_memmap_seg_iram0_6_max = 0x40000238;
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_memmap_seg_iram0_7_start = 0x40000238;
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_memmap_seg_iram0_7_max = 0x40000240;
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_memmap_seg_iram0_8_start = 0x40000240;
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_memmap_seg_iram0_8_max = 0x40000278;
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_memmap_seg_iram0_9_start = 0x40000278;
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_memmap_seg_iram0_9_max = 0x40000280;
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_memmap_seg_iram0_10_start = 0x40000280;
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_memmap_seg_iram0_10_max = 0x400002b8;
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_memmap_seg_iram0_11_start = 0x400002b8;
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_memmap_seg_iram0_11_max = 0x400002c0;
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_memmap_seg_iram0_12_start = 0x400002c0;
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_memmap_seg_iram0_12_max = 0x400002f8;
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_memmap_seg_iram0_13_start = 0x400002f8;
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_memmap_seg_iram0_13_max = 0x40000300;
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_memmap_seg_iram0_14_start = 0x40000300;
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_memmap_seg_iram0_14_max = 0x40000338;
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_memmap_seg_iram0_15_start = 0x40000338;
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_memmap_seg_iram0_15_max = 0x40000340;
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_memmap_seg_iram0_16_start = 0x40000340;
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_memmap_seg_iram0_16_max = 0x40000378;
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_memmap_seg_iram0_17_start = 0x40000378;
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_memmap_seg_iram0_17_max = 0x400003c0;
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_memmap_seg_iram0_18_start = 0x400003c0;
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_memmap_seg_iram0_18_max = 0x40000400;
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_memmap_seg_iram0_19_start = 0x40000400;
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_memmap_seg_iram0_19_max = 0x40020000;
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_memmap_seg_srom0_start = 0x50000000;
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_memmap_seg_srom0_max = 0x50000300;
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_memmap_seg_srom1_start = 0x50000300;
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_memmap_seg_srom1_max = 0x51000000;
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_memmap_seg_sram0_start = 0x60000000;
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_memmap_seg_sram0_max = 0x64000000;
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_rom_store_table = 0;
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PROVIDE(_memmap_vecbase_reset = 0x40000000);
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PROVIDE(_memmap_reset_vector = 0x50000000);
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/* Various memory-map dependent cache attribute settings: */
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_memmap_cacheattr_wb_base = 0x00001110;
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_memmap_cacheattr_wt_base = 0x00001110;
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_memmap_cacheattr_bp_base = 0x00002220;
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_memmap_cacheattr_unused_mask = 0xFFFF000F;
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_memmap_cacheattr_wb_trapnull = 0x2222111F;
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_memmap_cacheattr_wba_trapnull = 0x2222111F;
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_memmap_cacheattr_wbna_trapnull = 0x2222111F;
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_memmap_cacheattr_wt_trapnull = 0x2222111F;
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_memmap_cacheattr_bp_trapnull = 0x2222222F;
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_memmap_cacheattr_wb_strict = 0xFFFF111F;
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_memmap_cacheattr_wt_strict = 0xFFFF111F;
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_memmap_cacheattr_bp_strict = 0xFFFF222F;
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_memmap_cacheattr_wb_allvalid = 0x22221112;
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_memmap_cacheattr_wt_allvalid = 0x22221112;
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_memmap_cacheattr_bp_allvalid = 0x22222222;
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
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SECTIONS
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{
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.dram1.rodata : ALIGN(4)
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{
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_dram1_rodata_start = ABSOLUTE(.);
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*(.dram1.rodata)
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_dram1_rodata_end = ABSOLUTE(.);
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} >dram1_0_seg :dram1_0_phdr
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.dram1.literal : ALIGN(4)
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{
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_dram1_literal_start = ABSOLUTE(.);
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*(.dram1.literal)
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_dram1_literal_end = ABSOLUTE(.);
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} >dram1_0_seg :dram1_0_phdr
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.dram1.data : ALIGN(4)
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{
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_dram1_data_start = ABSOLUTE(.);
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*(.dram1.data)
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_dram1_data_end = ABSOLUTE(.);
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} >dram1_0_seg :dram1_0_phdr
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.dram1.bss (NOLOAD) : ALIGN(8)
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{
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. = ALIGN (8);
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_dram1_bss_start = ABSOLUTE(.);
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*(.dram1.bss)
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. = ALIGN (8);
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_dram1_bss_end = ABSOLUTE(.);
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_memmap_seg_dram1_0_end = ALIGN(0x8);
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} >dram1_0_seg :dram1_0_bss_phdr
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.dram0.rodata : ALIGN(4)
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{
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_dram0_rodata_start = ABSOLUTE(.);
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*(.dram0.rodata)
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_dram0_rodata_end = ABSOLUTE(.);
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} >dram0_0_seg :dram0_0_phdr
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.dram0.literal : ALIGN(4)
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{
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_dram0_literal_start = ABSOLUTE(.);
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*(.dram0.literal)
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_dram0_literal_end = ABSOLUTE(.);
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} >dram0_0_seg :dram0_0_phdr
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.dram0.data : ALIGN(4)
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{
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_dram0_data_start = ABSOLUTE(.);
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*(.dram0.data)
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_dram0_data_end = ABSOLUTE(.);
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} >dram0_0_seg :dram0_0_phdr
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.dram0.bss (NOLOAD) : ALIGN(8)
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{
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. = ALIGN (8);
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_dram0_bss_start = ABSOLUTE(.);
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*(.dram0.bss)
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. = ALIGN (8);
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_dram0_bss_end = ABSOLUTE(.);
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_memmap_seg_dram0_0_end = ALIGN(0x8);
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} >dram0_0_seg :dram0_0_bss_phdr
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.WindowVectors.text : ALIGN(4)
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{
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_WindowVectors_text_start = ABSOLUTE(.);
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KEEP (*(.WindowVectors.text))
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_WindowVectors_text_end = ABSOLUTE(.);
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_memmap_seg_iram0_0_end = ALIGN(0x8);
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} >iram0_0_seg :iram0_0_phdr
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.Level2InterruptVector.literal : ALIGN(4)
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{
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_Level2InterruptVector_literal_start = ABSOLUTE(.);
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*(.Level2InterruptVector.literal)
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_Level2InterruptVector_literal_end = ABSOLUTE(.);
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_memmap_seg_iram0_1_end = ALIGN(0x8);
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} >iram0_1_seg :iram0_1_phdr
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.Level2InterruptVector.text : ALIGN(4)
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{
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_Level2InterruptVector_text_start = ABSOLUTE(.);
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KEEP (*(.Level2InterruptVector.text))
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_Level2InterruptVector_text_end = ABSOLUTE(.);
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_memmap_seg_iram0_2_end = ALIGN(0x8);
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} >iram0_2_seg :iram0_2_phdr
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.Level3InterruptVector.literal : ALIGN(4)
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{
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_Level3InterruptVector_literal_start = ABSOLUTE(.);
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*(.Level3InterruptVector.literal)
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_Level3InterruptVector_literal_end = ABSOLUTE(.);
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_memmap_seg_iram0_3_end = ALIGN(0x8);
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} >iram0_3_seg :iram0_3_phdr
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.Level3InterruptVector.text : ALIGN(4)
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{
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_Level3InterruptVector_text_start = ABSOLUTE(.);
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KEEP (*(.Level3InterruptVector.text))
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_Level3InterruptVector_text_end = ABSOLUTE(.);
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_memmap_seg_iram0_4_end = ALIGN(0x8);
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} >iram0_4_seg :iram0_4_phdr
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.Level4InterruptVector.literal : ALIGN(4)
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{
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_Level4InterruptVector_literal_start = ABSOLUTE(.);
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*(.Level4InterruptVector.literal)
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_Level4InterruptVector_literal_end = ABSOLUTE(.);
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_memmap_seg_iram0_5_end = ALIGN(0x8);
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} >iram0_5_seg :iram0_5_phdr
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.Level4InterruptVector.text : ALIGN(4)
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{
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_Level4InterruptVector_text_start = ABSOLUTE(.);
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KEEP (*(.Level4InterruptVector.text))
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_Level4InterruptVector_text_end = ABSOLUTE(.);
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_memmap_seg_iram0_6_end = ALIGN(0x8);
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} >iram0_6_seg :iram0_6_phdr
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.Level5InterruptVector.literal : ALIGN(4)
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{
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_Level5InterruptVector_literal_start = ABSOLUTE(.);
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*(.Level5InterruptVector.literal)
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_Level5InterruptVector_literal_end = ABSOLUTE(.);
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_memmap_seg_iram0_7_end = ALIGN(0x8);
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} >iram0_7_seg :iram0_7_phdr
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.Level5InterruptVector.text : ALIGN(4)
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{
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_Level5InterruptVector_text_start = ABSOLUTE(.);
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KEEP (*(.Level5InterruptVector.text))
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_Level5InterruptVector_text_end = ABSOLUTE(.);
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_memmap_seg_iram0_8_end = ALIGN(0x8);
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} >iram0_8_seg :iram0_8_phdr
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.DebugExceptionVector.literal : ALIGN(4)
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{
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_DebugExceptionVector_literal_start = ABSOLUTE(.);
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*(.DebugExceptionVector.literal)
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_DebugExceptionVector_literal_end = ABSOLUTE(.);
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_memmap_seg_iram0_9_end = ALIGN(0x8);
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} >iram0_9_seg :iram0_9_phdr
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.DebugExceptionVector.text : ALIGN(4)
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{
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_DebugExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.DebugExceptionVector.text))
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_DebugExceptionVector_text_end = ABSOLUTE(.);
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_memmap_seg_iram0_10_end = ALIGN(0x8);
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} >iram0_10_seg :iram0_10_phdr
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.NMIExceptionVector.literal : ALIGN(4)
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{
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_NMIExceptionVector_literal_start = ABSOLUTE(.);
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*(.NMIExceptionVector.literal)
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_NMIExceptionVector_literal_end = ABSOLUTE(.);
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_memmap_seg_iram0_11_end = ALIGN(0x8);
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} >iram0_11_seg :iram0_11_phdr
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.NMIExceptionVector.text : ALIGN(4)
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{
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_NMIExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.NMIExceptionVector.text))
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_NMIExceptionVector_text_end = ABSOLUTE(.);
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_memmap_seg_iram0_12_end = ALIGN(0x8);
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} >iram0_12_seg :iram0_12_phdr
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.KernelExceptionVector.literal : ALIGN(4)
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{
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_KernelExceptionVector_literal_start = ABSOLUTE(.);
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*(.KernelExceptionVector.literal)
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_KernelExceptionVector_literal_end = ABSOLUTE(.);
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_memmap_seg_iram0_13_end = ALIGN(0x8);
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} >iram0_13_seg :iram0_13_phdr
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.KernelExceptionVector.text : ALIGN(4)
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{
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_KernelExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.KernelExceptionVector.text))
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_KernelExceptionVector_text_end = ABSOLUTE(.);
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_memmap_seg_iram0_14_end = ALIGN(0x8);
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} >iram0_14_seg :iram0_14_phdr
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.UserExceptionVector.literal : ALIGN(4)
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{
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_UserExceptionVector_literal_start = ABSOLUTE(.);
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*(.UserExceptionVector.literal)
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_UserExceptionVector_literal_end = ABSOLUTE(.);
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_memmap_seg_iram0_15_end = ALIGN(0x8);
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} >iram0_15_seg :iram0_15_phdr
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.UserExceptionVector.text : ALIGN(4)
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{
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_UserExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.UserExceptionVector.text))
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_UserExceptionVector_text_end = ABSOLUTE(.);
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_memmap_seg_iram0_16_end = ALIGN(0x8);
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} >iram0_16_seg :iram0_16_phdr
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.DoubleExceptionVector.literal : ALIGN(4)
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{
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_DoubleExceptionVector_literal_start = ABSOLUTE(.);
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*(.DoubleExceptionVector.literal)
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_DoubleExceptionVector_literal_end = ABSOLUTE(.);
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_memmap_seg_iram0_17_end = ALIGN(0x8);
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} >iram0_17_seg :iram0_17_phdr
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.DoubleExceptionVector.text : ALIGN(4)
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{
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_DoubleExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.DoubleExceptionVector.text))
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_DoubleExceptionVector_text_end = ABSOLUTE(.);
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_memmap_seg_iram0_18_end = ALIGN(0x8);
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} >iram0_18_seg :iram0_18_phdr
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.iram0.text : ALIGN(4)
|
|
{
|
|
_iram0_text_start = ABSOLUTE(.);
|
|
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
|
_iram0_text_end = ABSOLUTE(.);
|
|
_memmap_seg_iram0_19_end = ALIGN(0x8);
|
|
} >iram0_19_seg :iram0_19_phdr
|
|
|
|
.ResetVector.text : ALIGN(4)
|
|
{
|
|
_image_rom_start = ABSOLUTE(.);
|
|
_ResetVector_text_start = ABSOLUTE(.);
|
|
KEEP (*(.ResetVector.text))
|
|
_ResetVector_text_end = ABSOLUTE(.);
|
|
_memmap_seg_srom0_end = ALIGN(0x8);
|
|
} >srom0_seg :srom0_phdr
|
|
|
|
.srom.rodata : ALIGN(4)
|
|
{
|
|
_srom_rodata_start = ABSOLUTE(.);
|
|
*(.srom.rodata)
|
|
_srom_rodata_end = ABSOLUTE(.);
|
|
} >srom1_seg :srom1_phdr
|
|
|
|
.srom.text : ALIGN(4)
|
|
{
|
|
_srom_text_start = ABSOLUTE(.);
|
|
*(.srom.literal .srom.text)
|
|
_srom_text_end = ABSOLUTE(.);
|
|
_memmap_seg_srom1_end = ALIGN(0x8);
|
|
_image_rom_end = ABSOLUTE(.);
|
|
} >srom1_seg :srom1_phdr
|
|
|
|
.sram.rodata : ALIGN(4)
|
|
{
|
|
_image_ram_start = ABSOLUTE(.);
|
|
_sram_rodata_start = ABSOLUTE(.);
|
|
*(.sram.rodata)
|
|
_sram_rodata_end = ABSOLUTE(.);
|
|
} >sram0_seg :sram0_phdr
|
|
|
|
#include <linker/common-rom.ld>
|
|
|
|
.rodata : ALIGN(4)
|
|
{
|
|
_rodata_start = ABSOLUTE(.);
|
|
*(.rodata)
|
|
*(.rodata.*)
|
|
*(.gnu.linkonce.r.*)
|
|
*(.rodata1)
|
|
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
|
|
KEEP (*(.xt_except_table))
|
|
KEEP (*(.gcc_except_table))
|
|
*(.gnu.linkonce.e.*)
|
|
*(.gnu.version_r)
|
|
KEEP (*(.eh_frame))
|
|
/* C++ constructor and destructor tables, properly ordered: */
|
|
KEEP (*crtbegin.o(.ctors))
|
|
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
|
KEEP (*(SORT(.ctors.*)))
|
|
KEEP (*(.ctors))
|
|
KEEP (*crtbegin.o(.dtors))
|
|
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
|
KEEP (*(SORT(.dtors.*)))
|
|
KEEP (*(.dtors))
|
|
/* C++ exception handlers table: */
|
|
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
|
|
*(.xt_except_desc)
|
|
*(.gnu.linkonce.h.*)
|
|
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
|
*(.xt_except_desc_end)
|
|
*(.dynamic)
|
|
*(.gnu.version_d)
|
|
. = ALIGN(4); /* this table MUST be 4-byte aligned */
|
|
_bss_table_start = ABSOLUTE(.);
|
|
LONG(_dram1_bss_start)
|
|
LONG(_dram1_bss_end)
|
|
LONG(_dram0_bss_start)
|
|
LONG(_dram0_bss_end)
|
|
LONG(_bss_start)
|
|
LONG(_bss_end)
|
|
_bss_table_end = ABSOLUTE(.);
|
|
_rodata_end = ABSOLUTE(.);
|
|
} >sram0_seg :sram0_phdr
|
|
|
|
.sram.text : ALIGN(4)
|
|
{
|
|
_sram_text_start = ABSOLUTE(.);
|
|
*(.sram.literal .sram.text)
|
|
_sram_text_end = ABSOLUTE(.);
|
|
} >sram0_seg :sram0_phdr
|
|
|
|
_image_text_start = ALIGN(4);
|
|
.text : ALIGN(4)
|
|
{
|
|
_stext = .;
|
|
_text_start = ABSOLUTE(.);
|
|
*(.entry.text)
|
|
*(.init.literal)
|
|
KEEP(*(.init))
|
|
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
|
*(.fini.literal)
|
|
KEEP(*(.fini))
|
|
*(.gnu.version)
|
|
_text_end = ABSOLUTE(.);
|
|
_etext = .;
|
|
} >sram0_seg :sram0_phdr
|
|
_image_text_end = .;
|
|
|
|
.sram.data : ALIGN(4)
|
|
{
|
|
_sram_data_start = ABSOLUTE(.);
|
|
*(.sram.data)
|
|
_sram_data_end = ABSOLUTE(.);
|
|
} >sram0_seg :sram0_phdr
|
|
|
|
.noinit : ALIGN(4)
|
|
{
|
|
*(.noinit)
|
|
*(.noinit.*)
|
|
} >sram0_seg :sram0_phdr
|
|
|
|
.data : ALIGN(4)
|
|
{
|
|
_data_start = ABSOLUTE(.);
|
|
*(.data)
|
|
*(.data.*)
|
|
KEEP(*(SW_ISR_TABLE))
|
|
*(.gnu.linkonce.d.*)
|
|
KEEP(*(.gnu.linkonce.d.*personality*))
|
|
*(.data1)
|
|
*(.sdata)
|
|
*(.sdata.*)
|
|
*(.gnu.linkonce.s.*)
|
|
*(.sdata2)
|
|
*(.sdata2.*)
|
|
*(.gnu.linkonce.s2.*)
|
|
KEEP(*(.jcr))
|
|
_data_end = ABSOLUTE(.);
|
|
} >sram0_seg :sram0_phdr
|
|
|
|
#include <linker/common-ram.ld>
|
|
|
|
.bss (NOLOAD) : ALIGN(8)
|
|
{
|
|
. = ALIGN (8);
|
|
_bss_start = ABSOLUTE(.);
|
|
*(.dynsbss)
|
|
*(.sbss)
|
|
*(.sbss.*)
|
|
*(.gnu.linkonce.sb.*)
|
|
*(.scommon)
|
|
*(.sbss2)
|
|
*(.sbss2.*)
|
|
*(.gnu.linkonce.sb2.*)
|
|
*(.dynbss)
|
|
*(.bss)
|
|
*(.bss.*)
|
|
*(.gnu.linkonce.b.*)
|
|
*(COMMON)
|
|
*(.sram.bss)
|
|
. = ALIGN (8);
|
|
_bss_end = ABSOLUTE(.);
|
|
_end = ALIGN(0x8);
|
|
_image_ram_end = ABSOLUTE(.);
|
|
PROVIDE(end = ALIGN(0x8));
|
|
_stack_sentry = ALIGN(0x8);
|
|
_memmap_seg_sram0_end = ALIGN(0x8);
|
|
} >sram0_seg :sram0_bss_phdr
|
|
__stack = 0x64000000;
|
|
_heap_sentry = 0x64000000;
|
|
.debug 0 : { *(.debug) }
|
|
.line 0 : { *(.line) }
|
|
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
|
.debug_sfnames 0 : { *(.debug_sfnames) }
|
|
.debug_aranges 0 : { *(.debug_aranges) }
|
|
.debug_pubnames 0 : { *(.debug_pubnames) }
|
|
.debug_info 0 : { *(.debug_info) }
|
|
.debug_abbrev 0 : { *(.debug_abbrev) }
|
|
.debug_line 0 : { *(.debug_line) }
|
|
.debug_frame 0 : { *(.debug_frame) }
|
|
.debug_str 0 : { *(.debug_str) }
|
|
.debug_loc 0 : { *(.debug_loc) }
|
|
.debug_macinfo 0 : { *(.debug_macinfo) }
|
|
.debug_weaknames 0 : { *(.debug_weaknames) }
|
|
.debug_funcnames 0 : { *(.debug_funcnames) }
|
|
.debug_typenames 0 : { *(.debug_typenames) }
|
|
.debug_varnames 0 : { *(.debug_varnames) }
|
|
.xt.insn 0 :
|
|
{
|
|
KEEP (*(.xt.insn))
|
|
KEEP (*(.gnu.linkonce.x.*))
|
|
}
|
|
.xt.prop 0 :
|
|
{
|
|
KEEP (*(.xt.prop))
|
|
KEEP (*(.xt.prop.*))
|
|
KEEP (*(.gnu.linkonce.prop.*))
|
|
}
|
|
.xt.lit 0 :
|
|
{
|
|
KEEP (*(.xt.lit))
|
|
KEEP (*(.xt.lit.*))
|
|
KEEP (*(.gnu.linkonce.p.*))
|
|
}
|
|
.debug.xt.callgraph 0 :
|
|
{
|
|
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
|
|
}
|
|
#ifdef CONFIG_GEN_ISR_TABLES
|
|
#include <linker/intlist.ld>
|
|
#endif
|
|
}
|