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llext: disable for Harvard ARC variants

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Some ARC processor configurations have separate memory for code (ICCM)
and for data (DCCM). Such configurations are unsuitable for LLEXT,
except for some quite special cases. For now, disable LLEXT and its
tests for these devices completely.

Signed-off-by: Ilya Tagunov <Ilya.Tagunov@synopsys.com>
This commit is contained in:
Ilya Tagunov 2024-12-03 14:01:51 +00:00 • committed by Benjamin Cabé
commit ce50ea2f1f
3 changed files with 4 additions and 0 deletions
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2
doc/services/llext/index.rst
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@ -22,3 +22,5 @@ and introspected to some degree, as well as unloaded when no longer needed.
The LLEXT subsystem requires architecture-specific support. It is currently The LLEXT subsystem requires architecture-specific support. It is currently
available only on RISC-V, ARM, ARM64, ARC (experimental) and Xtensa cores. available only on RISC-V, ARM, ARM64, ARC (experimental) and Xtensa cores.
Harvard architecture cores that separate code and data paths and have no
common memory are not supported.

1
subsys/llext/Kconfig
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@ -5,6 +5,7 @@ menuconfig LLEXT
bool "Linkable loadable extensions" bool "Linkable loadable extensions"
select CACHE_MANAGEMENT if DCACHE select CACHE_MANAGEMENT if DCACHE
select KERNEL_WHOLE_ARCHIVE select KERNEL_WHOLE_ARCHIVE
depends on !HARVARD
help help
Enable the linkable loadable extension subsystem Enable the linkable loadable extension subsystem

1
tests/subsys/llext/simple/testcase.yaml
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@ -13,6 +13,7 @@ common:
- qemu_cortex_r5 # ARM Cortex-R5 (ARMv7-R ISA) - qemu_cortex_r5 # ARM Cortex-R5 (ARMv7-R ISA)
- mps2/an385 # ARM Cortex-M3 (ARMv7-M ISA) - mps2/an385 # ARM Cortex-M3 (ARMv7-M ISA)
- mps2/an521/cpu0 # ARM Cortex-M33 (ARMv8-M ISA) - mps2/an521/cpu0 # ARM Cortex-M33 (ARMv8-M ISA)
filter: not CONFIG_HARVARD
extra_configs: extra_configs:
- arch:arm64:CONFIG_LLEXT_HEAP_SIZE=128 - arch:arm64:CONFIG_LLEXT_HEAP_SIZE=128
extra_conf_files: extra_conf_files: