From ce50ea2f1fb5ab266808dac7b8da51f70ca4e30b Mon Sep 17 00:00:00 2001 From: Ilya Tagunov Date: Tue, 3 Dec 2024 14:01:51 +0000 Subject: [PATCH] llext: disable for Harvard ARC variants Some ARC processor configurations have separate memory for code (ICCM) and for data (DCCM). Such configurations are unsuitable for LLEXT, except for some quite special cases. For now, disable LLEXT and its tests for these devices completely. Signed-off-by: Ilya Tagunov --- doc/services/llext/index.rst | 2 ++ subsys/llext/Kconfig | 1 + tests/subsys/llext/simple/testcase.yaml | 1 + 3 files changed, 4 insertions(+) diff --git a/doc/services/llext/index.rst b/doc/services/llext/index.rst index ebae211d16d..ea63738ba3c 100644 --- a/doc/services/llext/index.rst +++ b/doc/services/llext/index.rst @@ -22,3 +22,5 @@ and introspected to some degree, as well as unloaded when no longer needed. The LLEXT subsystem requires architecture-specific support. It is currently available only on RISC-V, ARM, ARM64, ARC (experimental) and Xtensa cores. + Harvard architecture cores that separate code and data paths and have no + common memory are not supported. diff --git a/subsys/llext/Kconfig b/subsys/llext/Kconfig index 55800dcd0cf..0e3ce5dd57d 100644 --- a/subsys/llext/Kconfig +++ b/subsys/llext/Kconfig @@ -5,6 +5,7 @@ menuconfig LLEXT bool "Linkable loadable extensions" select CACHE_MANAGEMENT if DCACHE select KERNEL_WHOLE_ARCHIVE + depends on !HARVARD help Enable the linkable loadable extension subsystem diff --git a/tests/subsys/llext/simple/testcase.yaml b/tests/subsys/llext/simple/testcase.yaml index 23f31de6d06..bd48a6374f9 100644 --- a/tests/subsys/llext/simple/testcase.yaml +++ b/tests/subsys/llext/simple/testcase.yaml @@ -13,6 +13,7 @@ common: - qemu_cortex_r5 # ARM Cortex-R5 (ARMv7-R ISA) - mps2/an385 # ARM Cortex-M3 (ARMv7-M ISA) - mps2/an521/cpu0 # ARM Cortex-M33 (ARMv8-M ISA) + filter: not CONFIG_HARVARD extra_configs: - arch:arm64:CONFIG_LLEXT_HEAP_SIZE=128 extra_conf_files: