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drivers: timer: riscv_machine_timer: Add support for OpenTitan

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OpenTitan uses a timer compliant with the RISC-V privileged
specification.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
This commit is contained in:
Shawn Nematbakhsh 2023-01-13 15:22:57 -08:00 • committed by Stephanos Ioannidis
commit cd0f54fb88
3 changed files with 28 additions and 1 deletions
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3
drivers/timer/Kconfig.riscv_machine
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@ -10,7 +10,8 @@ config RISCV_MACHINE_TIMER
DT_HAS_NEORV32_MACHINE_TIMER_ENABLED || \ DT_HAS_NEORV32_MACHINE_TIMER_ENABLED || \
DT_HAS_NUCLEI_SYSTIMER_ENABLED || \ DT_HAS_NUCLEI_SYSTIMER_ENABLED || \
DT_HAS_SIFIVE_CLINT0_ENABLED || \ DT_HAS_SIFIVE_CLINT0_ENABLED || \
DT_HAS_TELINK_MACHINE_TIMER_ENABLED DT_HAS_TELINK_MACHINE_TIMER_ENABLED || \
DT_HAS_LOWRISC_MACHINE_TIMER_ENABLED
select TICKLESS_CAPABLE select TICKLESS_CAPABLE
select TIMER_HAS_64BIT_CYCLE_COUNTER select TIMER_HAS_64BIT_CYCLE_COUNTER
help help

7
drivers/timer/riscv_machine_timer.c
View file

@ -48,6 +48,13 @@
#define MTIME_REG DT_INST_REG_ADDR(0) #define MTIME_REG DT_INST_REG_ADDR(0)
#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 8) #define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 8)
#define TIMER_IRQN DT_INST_IRQN(0) #define TIMER_IRQN DT_INST_IRQN(0)
/* lowrisc,machine-timer */
#elif DT_HAS_COMPAT_STATUS_OKAY(lowrisc_machine_timer)
#define DT_DRV_COMPAT lowrisc_machine_timer
#define MTIME_REG (DT_INST_REG_ADDR(0) + 0x110)
#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 0x118)
#define TIMER_IRQN DT_INST_IRQN(0)
#endif #endif
#define CYC_PER_TICK ((uint32_t)((uint64_t) (sys_clock_hw_cycles_per_sec() \ #define CYC_PER_TICK ((uint32_t)((uint64_t) (sys_clock_hw_cycles_per_sec() \

19
dts/bindings/timer/lowrisc,machine-timer.yaml Normal file
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@ -0,0 +1,19 @@
# Copyright (c) 2023 Rivos Inc.
# SPDX-License-Identifier: Apache-2.0
description: |
OpenTitan Machine Timer
The OpenTitan machine timer provides RISC-V privileged mtime and mtimecmp
registers.
compatible: "lowrisc,machine-timer"
include: base.yaml
properties:
reg:
required: true
interrupts:
required: true