diff --git a/drivers/timer/Kconfig.riscv_machine b/drivers/timer/Kconfig.riscv_machine
index 6c1c72da31c..57578e9f1c0 100644
--- a/drivers/timer/Kconfig.riscv_machine
+++ b/drivers/timer/Kconfig.riscv_machine
@@ -10,7 +10,8 @@ config RISCV_MACHINE_TIMER
 		   DT_HAS_NEORV32_MACHINE_TIMER_ENABLED || \
 		   DT_HAS_NUCLEI_SYSTIMER_ENABLED || \
 		   DT_HAS_SIFIVE_CLINT0_ENABLED || \
-		   DT_HAS_TELINK_MACHINE_TIMER_ENABLED
+		   DT_HAS_TELINK_MACHINE_TIMER_ENABLED || \
+		   DT_HAS_LOWRISC_MACHINE_TIMER_ENABLED
 	select TICKLESS_CAPABLE
 	select TIMER_HAS_64BIT_CYCLE_COUNTER
 	help
diff --git a/drivers/timer/riscv_machine_timer.c b/drivers/timer/riscv_machine_timer.c
index be0d5362112..1b3a2ee1baa 100644
--- a/drivers/timer/riscv_machine_timer.c
+++ b/drivers/timer/riscv_machine_timer.c
@@ -48,6 +48,13 @@
 #define MTIME_REG	DT_INST_REG_ADDR(0)
 #define MTIMECMP_REG	(DT_INST_REG_ADDR(0) + 8)
 #define TIMER_IRQN	DT_INST_IRQN(0)
+/* lowrisc,machine-timer */
+#elif DT_HAS_COMPAT_STATUS_OKAY(lowrisc_machine_timer)
+#define DT_DRV_COMPAT lowrisc_machine_timer
+
+#define MTIME_REG	(DT_INST_REG_ADDR(0) + 0x110)
+#define MTIMECMP_REG	(DT_INST_REG_ADDR(0) + 0x118)
+#define TIMER_IRQN	DT_INST_IRQN(0)
 #endif
 
 #define CYC_PER_TICK ((uint32_t)((uint64_t) (sys_clock_hw_cycles_per_sec()			 \
diff --git a/dts/bindings/timer/lowrisc,machine-timer.yaml b/dts/bindings/timer/lowrisc,machine-timer.yaml
new file mode 100644
index 00000000000..01721e22ed4
--- /dev/null
+++ b/dts/bindings/timer/lowrisc,machine-timer.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2023 Rivos Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  OpenTitan Machine Timer
+
+  The OpenTitan machine timer provides RISC-V privileged mtime and mtimecmp
+  registers.
+
+compatible: "lowrisc,machine-timer"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true