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Convert remaining code to using newly introduced integer sized types

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Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.  This handles the remaining includes and kernel, plus
touching up various points that we skipped because of include
dependancies.  We also convert the PRI printf formatters in the arch
code over to normal formatters.

Jira: ZEP-2051

Change-Id: Iecbb12601a3ee4ea936fd7ddea37788a645b08b0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-04-21 10:55:34 -05:00
commit cc334c7273
132 changed files with 1420 additions and 1429 deletions
Download patch file Download diff file Expand all files Collapse all files

74
include/arch/arc/v2/asm_inline_gcc.h
View file

@ -24,43 +24,43 @@ extern "C" {
/**
* @brief read timestamp register (CPU frequency)
*/
extern uint64_t _tsc_read(void);
extern u64_t _tsc_read(void);
/* Implementation of sys_io.h's documented functions */
static ALWAYS_INLINE
void sys_out8(uint8_t data, io_port_t port)
void sys_out8(u8_t data, io_port_t port)
{
_arc_v2_aux_reg_write(port, data);
}
static ALWAYS_INLINE
uint8_t sys_in8(io_port_t port)
u8_t sys_in8(io_port_t port)
{
return (uint8_t)(_arc_v2_aux_reg_read(port) & 0x000000ff);
return (u8_t)(_arc_v2_aux_reg_read(port) & 0x000000ff);
}
static ALWAYS_INLINE
void sys_out16(uint16_t data, io_port_t port)
void sys_out16(u16_t data, io_port_t port)
{
_arc_v2_aux_reg_write(port, data);
}
static ALWAYS_INLINE
uint16_t sys_in16(io_port_t port)
u16_t sys_in16(io_port_t port)
{
return (uint16_t)(_arc_v2_aux_reg_read(port) & 0x0000ffff);
return (u16_t)(_arc_v2_aux_reg_read(port) & 0x0000ffff);
}
static ALWAYS_INLINE
void sys_out32(uint32_t data, io_port_t port)
void sys_out32(u32_t data, io_port_t port)
{
_arc_v2_aux_reg_write(port, data);
}
static ALWAYS_INLINE
uint32_t sys_in32(io_port_t port)
u32_t sys_in32(io_port_t port)
{
return _arc_v2_aux_reg_read(port);
}
@ -68,7 +68,7 @@ static ALWAYS_INLINE
static ALWAYS_INLINE
void sys_io_set_bit(io_port_t port, unsigned int bit)
{
uint32_t reg = 0;
u32_t reg = 0;
__asm__ volatile("lr %1, [%0]\n"
"bset %1, %1, %2\n"
@ -82,7 +82,7 @@ static ALWAYS_INLINE
static ALWAYS_INLINE
void sys_io_clear_bit(io_port_t port, unsigned int bit)
{
uint32_t reg = 0;
u32_t reg = 0;
__asm__ volatile("lr %1, [%0]\n"
"bclr %1, %1, %2\n"
@ -96,9 +96,9 @@ static ALWAYS_INLINE
static ALWAYS_INLINE
int sys_io_test_bit(io_port_t port, unsigned int bit)
{
uint32_t status = _ARC_V2_STATUS32;
uint32_t reg = 0;
uint32_t ret;
u32_t status = _ARC_V2_STATUS32;
u32_t reg = 0;
u32_t ret;
__asm__ volatile("lr %2, [%1]\n"
"btst %2, %3\n"
@ -134,66 +134,66 @@ static ALWAYS_INLINE
}
static ALWAYS_INLINE
void sys_write8(uint8_t data, mm_reg_t addr)
void sys_write8(u8_t data, mm_reg_t addr)
{
__asm__ volatile("stb%U1 %0, %1;\n\t"
:
: "r" (data), "m" (*(volatile uint8_t *) addr)
: "r" (data), "m" (*(volatile u8_t *) addr)
: "memory");
}
static ALWAYS_INLINE
uint8_t sys_read8(mm_reg_t addr)
u8_t sys_read8(mm_reg_t addr)
{
uint8_t ret;
u8_t ret;
__asm__ volatile("ldb%U1 %0, %1;\n\t"
: "=r" (ret)
: "m" (*(volatile uint8_t *) addr)
: "m" (*(volatile u8_t *) addr)
: "memory");
return ret;
}
static ALWAYS_INLINE
void sys_write16(uint16_t data, mm_reg_t addr)
void sys_write16(u16_t data, mm_reg_t addr)
{
__asm__ volatile("sth%U1 %0, %1;\n\t"
:
: "r" (data), "m" (*(volatile uint16_t *) addr)
: "r" (data), "m" (*(volatile u16_t *) addr)
: "memory");
}
static ALWAYS_INLINE
uint16_t sys_read16(mm_reg_t addr)
u16_t sys_read16(mm_reg_t addr)
{
uint16_t ret;
u16_t ret;
__asm__ volatile("ldh%U1 %0, %1;\n\t"
: "=r" (ret)
: "m" (*(volatile uint16_t *) addr)
: "m" (*(volatile u16_t *) addr)
: "memory");
return ret;
}
static ALWAYS_INLINE
void sys_write32(uint32_t data, mm_reg_t addr)
void sys_write32(u32_t data, mm_reg_t addr)
{
__asm__ volatile("st%U1 %0, %1;\n\t"
:
: "r" (data), "m" (*(volatile uint32_t *) addr)
: "r" (data), "m" (*(volatile u32_t *) addr)
: "memory");
}
static ALWAYS_INLINE
uint32_t sys_read32(mm_reg_t addr)
u32_t sys_read32(mm_reg_t addr)
{
uint32_t ret;
u32_t ret;
__asm__ volatile("ld%U1 %0, %1;\n\t"
: "=r" (ret)
: "m" (*(volatile uint32_t *) addr)
: "m" (*(volatile u32_t *) addr)
: "memory");
return ret;
@ -202,12 +202,12 @@ static ALWAYS_INLINE
static ALWAYS_INLINE
void sys_set_bit(mem_addr_t addr, unsigned int bit)
{
uint32_t reg = 0;
u32_t reg = 0;
__asm__ volatile("ld %1, %0\n"
"bset %1, %1, %2\n"
"st %1, %0;\n\t"
: "+m" (*(volatile uint32_t *) addr)
: "+m" (*(volatile u32_t *) addr)
: "r" (reg), "Mr" (bit)
: "memory", "cc");
}
@ -215,12 +215,12 @@ static ALWAYS_INLINE
static ALWAYS_INLINE
void sys_clear_bit(mem_addr_t addr, unsigned int bit)
{
uint32_t reg = 0;
u32_t reg = 0;
__asm__ volatile("ld %1, %0\n"
"bclr %1, %1, %2\n"
"st %1, %0;\n\t"
: "+m" (*(volatile uint32_t *) addr)
: "+m" (*(volatile u32_t *) addr)
: "r" (reg), "Mr" (bit)
: "memory", "cc");
}
@ -228,15 +228,15 @@ static ALWAYS_INLINE
static ALWAYS_INLINE
int sys_test_bit(mem_addr_t addr, unsigned int bit)
{
uint32_t status = _ARC_V2_STATUS32;
uint32_t reg = 0;
uint32_t ret;
u32_t status = _ARC_V2_STATUS32;
u32_t reg = 0;
u32_t ret;
__asm__ volatile("ld %2, %1\n"
"btst %2, %3\n"
"lr %0, [%4];\n\t"
: "=r" (ret)
: "m" (*(volatile uint32_t *) addr),
: "m" (*(volatile u32_t *) addr),
"r" (reg), "Mr" (bit), "i" (status)
: "memory", "cc");

4
include/arch/arc/v2/aux_regs.h
View file

@ -113,8 +113,8 @@ extern "C" {
#if defined(__GNUC__)
#include <zephyr/types.h>
#define _arc_v2_aux_reg_read(reg) __builtin_arc_lr((volatile uint32_t)reg)
#define _arc_v2_aux_reg_write(reg, val) __builtin_arc_sr((unsigned int)val, (volatile uint32_t)reg)
#define _arc_v2_aux_reg_read(reg) __builtin_arc_lr((volatile u32_t)reg)
#define _arc_v2_aux_reg_write(reg, val) __builtin_arc_sr((unsigned int)val, (volatile u32_t)reg)
#else /* ! __GNUC__ */

4
include/arch/arc/v2/ffs.h
View file

@ -35,7 +35,7 @@ extern "C" {
*/
#if defined(__GNUC__)
static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_msb_set(u32_t op)
{
unsigned int bit;
@ -64,7 +64,7 @@ static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
*/
#if defined(__GNUC__)
static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_lsb_set(u32_t op)
{
unsigned int bit;

2
include/arch/arc/v2/irq.h
View file

@ -35,7 +35,7 @@ extern void _arch_irq_disable(unsigned int irq);
extern void _irq_exit(void);
extern void _irq_priority_set(unsigned int irq, unsigned int prio,
uint32_t flags);
u32_t flags);
extern void _isr_wrapper(void);
extern void _irq_spurious(void *unused);

2
include/arch/arc/v2/misc.h
View file

@ -23,7 +23,7 @@ extern unsigned int k_cpu_sleep_mode;
extern void k_cpu_idle(void);
extern void k_cpu_atomic_idle(unsigned int key);
extern uint32_t _timer_cycle_get_32(void);
extern u32_t _timer_cycle_get_32(void);
#define _arch_k_cycle_get_32() _timer_cycle_get_32()
#endif

2
include/arch/arm/arch.h
View file

@ -24,7 +24,7 @@ extern "C" {
#endif
/* ARM GPRs are often designated by two different names */
#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; }
#define sys_define_gpr_with_alias(name1, name2) union { u32_t name1, name2; }
/* APIs need to support non-byte addressable architectures */

4
include/arch/arm/cortex_m/asm_inline_gcc.h
View file

@ -45,7 +45,7 @@ extern "C" {
* @return most significant bit set, 0 if @a op is 0
*/
static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_msb_set(u32_t op)
{
if (!op) {
return 0;
@ -67,7 +67,7 @@ static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
* @return least significant bit set, 0 if @a op is 0
*/
static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_lsb_set(u32_t op)
{
return __builtin_ffs(op);
}

6
include/arch/arm/cortex_m/cmsis.h
View file

@ -36,9 +36,9 @@ extern "C" {
#define CPACR_CP11_RESERVED (2UL << CPACR_CP11_Pos)
#define CPACR_CP11_FULL_ACCESS (3UL << CPACR_CP11_Pos)
#define SCB_UFSR (*((__IOM uint16_t *) &SCB->CFSR + 2))
#define SCB_BFSR (*((__IOM uint8_t *) &SCB->CFSR + 1))
#define SCB_MMFSR (*((__IOM uint8_t *) &SCB->CFSR))
#define SCB_UFSR (*((__IOM u16_t *) &SCB->CFSR + 2))
#define SCB_BFSR (*((__IOM u8_t *) &SCB->CFSR + 1))
#define SCB_MMFSR (*((__IOM u8_t *) &SCB->CFSR))
/* CFSR[UFSR] */
#define CFSR_DIVBYZERO_Pos (25U)

6
include/arch/arm/cortex_m/exc.h
View file

@ -53,11 +53,11 @@ struct __esf {
sys_define_gpr_with_alias(ip, r12);
sys_define_gpr_with_alias(lr, r14);
sys_define_gpr_with_alias(pc, r15);
uint32_t xpsr;
u32_t xpsr;
#ifdef CONFIG_FLOAT
float s[16];
uint32_t fpscr;
uint32_t undefined;
u32_t fpscr;
u32_t undefined;
#endif
};

2
include/arch/arm/cortex_m/irq.h
View file

@ -43,7 +43,7 @@ extern void _IntExit(void);
/* internal routine documented in C file, needed by IRQ_CONNECT() macro */
extern void _irq_priority_set(unsigned int irq, unsigned int prio,
uint32_t flags);
u32_t flags);
/* Flags for use with IRQ_CONNECT() */

2
include/arch/arm/cortex_m/misc.h
View file

@ -21,7 +21,7 @@ extern "C" {
#ifndef _ASMLANGUAGE
extern void k_cpu_idle(void);
extern uint32_t _timer_cycle_get_32(void);
extern u32_t _timer_cycle_get_32(void);
#define _arch_k_cycle_get_32() _timer_cycle_get_32()
#endif

16
include/arch/arm/cortex_m/sys_io.h
View file

@ -17,15 +17,15 @@
/* Memory mapped registers I/O functions */
static inline uint32_t sys_read32(mem_addr_t addr)
static inline u32_t sys_read32(mem_addr_t addr)
{
return *(volatile uint32_t *)addr;
return *(volatile u32_t *)addr;
}
static inline void sys_write32(uint32_t data, mem_addr_t addr)
static inline void sys_write32(u32_t data, mem_addr_t addr)
{
*(volatile uint32_t *)addr = data;
*(volatile u32_t *)addr = data;
}
@ -33,16 +33,16 @@ static inline void sys_write32(uint32_t data, mem_addr_t addr)
static inline void sys_set_bit(mem_addr_t addr, unsigned int bit)
{
uint32_t temp = *(volatile uint32_t *)addr;
u32_t temp = *(volatile u32_t *)addr;
*(volatile uint32_t *)addr = temp | (1 << bit);
*(volatile u32_t *)addr = temp | (1 << bit);
}
static inline void sys_clear_bit(mem_addr_t addr, unsigned int bit)
{
uint32_t temp = *(volatile uint32_t *)addr;
u32_t temp = *(volatile u32_t *)addr;
*(volatile uint32_t *)addr = temp & ~(1 << bit);
*(volatile u32_t *)addr = temp & ~(1 << bit);
}
#endif /* !_ASMLANGUAGE */

38
include/arch/nios2/arch.h
View file

@ -131,24 +131,24 @@ void _arch_irq_enable(unsigned int irq);
void _arch_irq_disable(unsigned int irq);
struct __esf {
uint32_t ra; /* return address r31 */
uint32_t r1; /* at */
uint32_t r2; /* return value */
uint32_t r3; /* return value */
uint32_t r4; /* register args */
uint32_t r5; /* register args */
uint32_t r6; /* register args */
uint32_t r7; /* register args */
uint32_t r8; /* Caller-saved general purpose */
uint32_t r9; /* Caller-saved general purpose */
uint32_t r10; /* Caller-saved general purpose */
uint32_t r11; /* Caller-saved general purpose */
uint32_t r12; /* Caller-saved general purpose */
uint32_t r13; /* Caller-saved general purpose */
uint32_t r14; /* Caller-saved general purpose */
uint32_t r15; /* Caller-saved general purpose */
uint32_t estatus;
uint32_t instr; /* Instruction being executed when exc occurred */
u32_t ra; /* return address r31 */
u32_t r1; /* at */
u32_t r2; /* return value */
u32_t r3; /* return value */
u32_t r4; /* register args */
u32_t r5; /* register args */
u32_t r6; /* register args */
u32_t r7; /* register args */
u32_t r8; /* Caller-saved general purpose */
u32_t r9; /* Caller-saved general purpose */
u32_t r10; /* Caller-saved general purpose */
u32_t r11; /* Caller-saved general purpose */
u32_t r12; /* Caller-saved general purpose */
u32_t r13; /* Caller-saved general purpose */
u32_t r14; /* Caller-saved general purpose */
u32_t r15; /* Caller-saved general purpose */
u32_t estatus;
u32_t instr; /* Instruction being executed when exc occurred */
};
typedef struct __esf NANO_ESF;
@ -199,7 +199,7 @@ enum nios2_exception_cause {
BIT(NIOS2_EXCEPTION_ECC_DATA_ERR))
extern uint32_t _timer_cycle_get_32(void);
extern u32_t _timer_cycle_get_32(void);
#define _arch_k_cycle_get_32() _timer_cycle_get_32()
#endif /* _ASMLANGUAGE */

16
include/arch/nios2/asm_inline_gcc.h
View file

@ -32,7 +32,7 @@ extern "C" {
* @return most significant bit set, 0 if @a op is 0
*/
static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_msb_set(u32_t op)
{
if (!op)
return 0;
@ -51,7 +51,7 @@ static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
* @return least significant bit set, 0 if @a op is 0
*/
static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_lsb_set(u32_t op)
{
return __builtin_ffs(op);
}
@ -61,37 +61,37 @@ static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
*/
static ALWAYS_INLINE
void sys_write32(uint32_t data, mm_reg_t addr)
void sys_write32(u32_t data, mm_reg_t addr)
{
__builtin_stwio((void *)addr, data);
}
static ALWAYS_INLINE
uint32_t sys_read32(mm_reg_t addr)
u32_t sys_read32(mm_reg_t addr)
{
return __builtin_ldwio((void *)addr);
}
static ALWAYS_INLINE
void sys_write8(uint8_t data, mm_reg_t addr)
void sys_write8(u8_t data, mm_reg_t addr)
{
sys_write32(data, addr);
}
static ALWAYS_INLINE
uint8_t sys_read8(mm_reg_t addr)
u8_t sys_read8(mm_reg_t addr)
{
return __builtin_ldbuio((void *)addr);
}
static ALWAYS_INLINE
void sys_write16(uint16_t data, mm_reg_t addr)
void sys_write16(u16_t data, mm_reg_t addr)
{
sys_write32(data, addr);
}
static ALWAYS_INLINE
uint16_t sys_read16(mm_reg_t addr)
u16_t sys_read16(mm_reg_t addr)
{
return __builtin_ldhuio((void *)addr);
}

22
include/arch/nios2/nios2.h
View file

@ -60,22 +60,22 @@ extern "C"
*/
/* ET (Exception Temporary) register */
static inline uint32_t _nios2_read_et(void)
static inline u32_t _nios2_read_et(void)
{
uint32_t et;
u32_t et;
__asm__("mov %0, et" : "=r" (et));
return et;
}
static inline void _nios2_write_et(uint32_t et)
static inline void _nios2_write_et(u32_t et)
{
__asm__ volatile("mov et, %z0" : : "rM" (et));
}
static inline uint32_t _nios2_read_sp(void)
static inline u32_t _nios2_read_sp(void)
{
uint32_t sp;
u32_t sp;
__asm__("mov %0, sp" : "=r" (sp));
return sp;
@ -102,12 +102,12 @@ static inline void _nios2_dcache_addr_flush(void *addr)
__asm__ volatile ("flushda (%0)" :: "r" (addr));
}
static inline void _nios2_dcache_flush(uint32_t offset)
static inline void _nios2_dcache_flush(u32_t offset)
{
__asm__ volatile ("flushd (%0)" :: "r" (offset));
}
static inline void _nios2_icache_flush(uint32_t offset)
static inline void _nios2_icache_flush(u32_t offset)
{
__asm__ volatile ("flushi %0" :: "r" (offset));
}
@ -145,7 +145,7 @@ enum nios2_creg {
* we get errors "Control register number must be in range 0-31 for
* __builtin_rdctl" with the following code:
*
* static inline uint32_t _nios2_creg_read(enum nios2_creg reg)
* static inline u32_t _nios2_creg_read(enum nios2_creg reg)
* {
* return __builtin_rdctl(reg);
* }
@ -156,14 +156,14 @@ enum nios2_creg {
#define _nios2_creg_write(reg, val) __builtin_wrctl(reg, val)
#define _nios2_get_register_address(base, regnum) \
((void *)(((uint8_t *)base) + ((regnum) * (SYSTEM_BUS_WIDTH / 8))))
((void *)(((u8_t *)base) + ((regnum) * (SYSTEM_BUS_WIDTH / 8))))
static inline void _nios2_reg_write(void *base, int regnum, uint32_t data)
static inline void _nios2_reg_write(void *base, int regnum, u32_t data)
{
sys_write32(data, (mm_reg_t)_nios2_get_register_address(base, regnum));
}
static inline uint32_t _nios2_reg_read(void *base, int regnum)
static inline u32_t _nios2_reg_read(void *base, int regnum)
{
return sys_read32((mm_reg_t)_nios2_get_register_address(base, regnum));
}

4
include/arch/riscv32/arch.h
View file

@ -51,7 +51,7 @@ extern "C" {
* SOC-specific function to get the IRQ number generating the interrupt.
* __soc_get_irq returns a bitfield of pending IRQs.
*/
extern uint32_t __soc_get_irq(void);
extern u32_t __soc_get_irq(void);
void _arch_irq_enable(unsigned int irq);
void _arch_irq_disable(unsigned int irq);
@ -118,7 +118,7 @@ static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
: "memory");
}
extern uint32_t _timer_cycle_get_32(void);
extern u32_t _timer_cycle_get_32(void);
#define _arch_k_cycle_get_32() _timer_cycle_get_32()
#endif /*_ASMLANGUAGE */

52
include/arch/riscv32/exp.h
View file

@ -23,38 +23,38 @@ extern "C" {
#include <toolchain.h>
struct __esf {
uint32_t ra; /* return address */
uint32_t gp; /* global pointer */
uint32_t tp; /* thread pointer */
u32_t ra; /* return address */
u32_t gp; /* global pointer */
u32_t tp; /* thread pointer */
uint32_t t0; /* Caller-saved temporary register */
uint32_t t1; /* Caller-saved temporary register */
uint32_t t2; /* Caller-saved temporary register */
uint32_t t3; /* Caller-saved temporary register */
uint32_t t4; /* Caller-saved temporary register */
uint32_t t5; /* Caller-saved temporary register */
uint32_t t6; /* Caller-saved temporary register */
u32_t t0; /* Caller-saved temporary register */
u32_t t1; /* Caller-saved temporary register */
u32_t t2; /* Caller-saved temporary register */
u32_t t3; /* Caller-saved temporary register */
u32_t t4; /* Caller-saved temporary register */
u32_t t5; /* Caller-saved temporary register */
u32_t t6; /* Caller-saved temporary register */
uint32_t a0; /* function argument/return value */
uint32_t a1; /* function argument */
uint32_t a2; /* function argument */
uint32_t a3; /* function argument */
uint32_t a4; /* function argument */
uint32_t a5; /* function argument */
uint32_t a6; /* function argument */
uint32_t a7; /* function argument */
u32_t a0; /* function argument/return value */
u32_t a1; /* function argument */
u32_t a2; /* function argument */
u32_t a3; /* function argument */
u32_t a4; /* function argument */
u32_t a5; /* function argument */
u32_t a6; /* function argument */
u32_t a7; /* function argument */
uint32_t mepc; /* machine exception program counter */
uint32_t mstatus; /* machine status register */
u32_t mepc; /* machine exception program counter */
u32_t mstatus; /* machine status register */
#if defined(CONFIG_SOC_RISCV32_PULPINO)
/* pulpino hardware loop registers */
uint32_t lpstart0;
uint32_t lpend0;
uint32_t lpcount0;
uint32_t lpstart1;
uint32_t lpend1;
uint32_t lpcount1;
u32_t lpstart0;
u32_t lpend0;
u32_t lpcount0;
u32_t lpstart1;
u32_t lpend1;
u32_t lpcount1;
#endif
};

4
include/arch/riscv32/fe310/asm_inline_gcc.h
View file

@ -32,7 +32,7 @@ extern "C" {
*
* @return least significant bit set, 0 if @a op is 0
*/
static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_lsb_set(u32_t op)
{
return __builtin_ffs(op);
}
@ -48,7 +48,7 @@ static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
*
* @return most significant bit set, 0 if @a op is 0
*/
static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_msb_set(u32_t op)
{
if (!op)
return 0;

8
include/arch/riscv32/pulpino/asm_inline_gcc.h
View file

@ -38,7 +38,7 @@ extern "C" {
*
* @return least significant bit set, 0 if @a op is 0
*/
static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_lsb_set(u32_t op)
{
unsigned int ret;
@ -63,7 +63,7 @@ static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
*
* @return most significant bit set, 0 if @a op is 0
*/
static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_msb_set(u32_t op)
{
unsigned int ret;
@ -84,12 +84,12 @@ static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
* __builtin_ffs and __builtin_clz to handle respectively
* find_lsb_set and find_msb_set.
*/
static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_lsb_set(u32_t op)
{
return __builtin_ffs(op);
}
static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_msb_set(u32_t op)
{
if (!op)
return 0;

4
include/arch/riscv32/riscv32-qemu/asm_inline_gcc.h
View file

@ -33,7 +33,7 @@ extern "C" {
*
* @return least significant bit set, 0 if @a op is 0
*/
static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_lsb_set(u32_t op)
{
return __builtin_ffs(op);
}
@ -49,7 +49,7 @@ static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
*
* @return most significant bit set, 0 if @a op is 0
*/
static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_msb_set(u32_t op)
{
if (!op)
return 0;

26
include/arch/riscv32/sys_io.h
View file

@ -17,47 +17,47 @@
/* Memory mapped registers I/O functions */
static inline uint32_t sys_read32(mem_addr_t addr)
static inline u32_t sys_read32(mem_addr_t addr)
{
return *(volatile uint32_t *)addr;
return *(volatile u32_t *)addr;
}
static inline void sys_write32(uint32_t data, mem_addr_t addr)
static inline void sys_write32(u32_t data, mem_addr_t addr)
{
*(volatile uint32_t *)addr = data;
*(volatile u32_t *)addr = data;
}
static inline uint8_t sys_read8(mem_addr_t addr)
static inline u8_t sys_read8(mem_addr_t addr)
{
return *(volatile uint8_t *)addr;
return *(volatile u8_t *)addr;
}
static inline void sys_write8(uint8_t data, mem_addr_t addr)
static inline void sys_write8(u8_t data, mem_addr_t addr)
{
*(volatile uint8_t *)addr = data;
*(volatile u8_t *)addr = data;
}
/* Memory bit manipulation functions */
static inline void sys_set_bit(mem_addr_t addr, unsigned int bit)
{
uint32_t temp = *(volatile uint32_t *)addr;
u32_t temp = *(volatile u32_t *)addr;
*(volatile uint32_t *)addr = temp | (1 << bit);
*(volatile u32_t *)addr = temp | (1 << bit);
}
static inline void sys_clear_bit(mem_addr_t addr, unsigned int bit)
{
uint32_t temp = *(volatile uint32_t *)addr;
u32_t temp = *(volatile u32_t *)addr;
*(volatile uint32_t *)addr = temp & ~(1 << bit);
*(volatile u32_t *)addr = temp & ~(1 << bit);
}
static ALWAYS_INLINE
int sys_test_bit(mem_addr_t addr, unsigned int bit)
{
uint32_t temp = *(volatile uint32_t *)addr;
u32_t temp = *(volatile u32_t *)addr;
return temp & (1 << bit);
}

2
include/arch/x86/arch.h
View file

@ -488,7 +488,7 @@ extern void k_float_disable(k_tid_t thread);
extern void k_cpu_idle(void);
extern uint32_t _timer_cycle_get_32(void);
extern u32_t _timer_cycle_get_32(void);
#define _arch_k_cycle_get_32() _timer_cycle_get_32()
/** kernel provided routine to report any detected fatal error. */

80
include/arch/x86/asm_inline_gcc.h
View file

@ -96,7 +96,7 @@ static ALWAYS_INLINE void _do_irq_unlock(void)
* after the 'cmovzl', the correct results are yielded.
*/
static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_lsb_set(u32_t op)
{
unsigned int bitpos;
@ -146,7 +146,7 @@ static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
* after the 'cmovzl', the correct results are yielded.
*/
static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_msb_set(u32_t op)
{
unsigned int bitpos;
@ -180,14 +180,14 @@ static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
* @brief read timestamp register ensuring serialization
*/
static inline uint64_t _tsc_read(void)
static inline u64_t _tsc_read(void)
{
union {
struct {
uint32_t lo;
uint32_t hi;
u32_t lo;
u32_t hi;
};
uint64_t value;
u64_t value;
} rv;
/* rdtsc & cpuid clobbers eax, ebx, ecx and edx registers */
@ -217,9 +217,9 @@ static inline uint64_t _tsc_read(void)
*/
static ALWAYS_INLINE
uint32_t _do_read_cpu_timestamp32(void)
u32_t _do_read_cpu_timestamp32(void)
{
uint32_t rv;
u32_t rv;
__asm__ volatile("rdtsc" : "=a"(rv) : : "%edx");
@ -230,7 +230,7 @@ static ALWAYS_INLINE
/* Implementation of sys_io.h's documented functions */
static ALWAYS_INLINE
void sys_out8(uint8_t data, io_port_t port)
void sys_out8(u8_t data, io_port_t port)
{
__asm__ volatile("outb %b0, %w1;\n\t"
:
@ -239,9 +239,9 @@ void sys_out8(uint8_t data, io_port_t port)
static ALWAYS_INLINE
uint8_t sys_in8(io_port_t port)
u8_t sys_in8(io_port_t port)
{
uint8_t ret;
u8_t ret;
__asm__ volatile("inb %w1, %b0;\n\t"
: "=a"(ret)
@ -251,7 +251,7 @@ static ALWAYS_INLINE
static ALWAYS_INLINE
void sys_out16(uint16_t data, io_port_t port)
void sys_out16(u16_t data, io_port_t port)
{
__asm__ volatile("outw %w0, %w1;\n\t"
:
@ -260,9 +260,9 @@ static ALWAYS_INLINE
static ALWAYS_INLINE
uint16_t sys_in16(io_port_t port)
u16_t sys_in16(io_port_t port)
{
uint16_t ret;
u16_t ret;
__asm__ volatile("inw %w1, %w0;\n\t"
: "=a"(ret)
@ -272,7 +272,7 @@ static ALWAYS_INLINE
static ALWAYS_INLINE
void sys_out32(uint32_t data, io_port_t port)
void sys_out32(u32_t data, io_port_t port)
{
__asm__ volatile("outl %0, %w1;\n\t"
:
@ -281,9 +281,9 @@ static ALWAYS_INLINE
static ALWAYS_INLINE
uint32_t sys_in32(io_port_t port)
u32_t sys_in32(io_port_t port)
{
uint32_t ret;
u32_t ret;
__asm__ volatile("inl %w1, %0;\n\t"
: "=a"(ret)
@ -295,7 +295,7 @@ static ALWAYS_INLINE
static ALWAYS_INLINE
void sys_io_set_bit(io_port_t port, unsigned int bit)
{
uint32_t reg = 0;
u32_t reg = 0;
__asm__ volatile("inl %w1, %0;\n\t"
"btsl %2, %0;\n\t"
@ -307,7 +307,7 @@ static ALWAYS_INLINE
static ALWAYS_INLINE
void sys_io_clear_bit(io_port_t port, unsigned int bit)
{
uint32_t reg = 0;
u32_t reg = 0;
__asm__ volatile("inl %w1, %0;\n\t"
"btrl %2, %0;\n\t"
@ -319,7 +319,7 @@ static ALWAYS_INLINE
static ALWAYS_INLINE
int sys_io_test_bit(io_port_t port, unsigned int bit)
{
uint32_t ret;
u32_t ret;
__asm__ volatile("inl %w1, %0\n\t"
"btl %2, %0\n\t"
@ -352,66 +352,66 @@ static ALWAYS_INLINE
}
static ALWAYS_INLINE
void sys_write8(uint8_t data, mm_reg_t addr)
void sys_write8(u8_t data, mm_reg_t addr)
{
__asm__ volatile("movb %0, %1;\n\t"
:
: "q"(data), "m" (*(volatile uint8_t *) addr)
: "q"(data), "m" (*(volatile u8_t *) addr)
: "memory");
}
static ALWAYS_INLINE
uint8_t sys_read8(mm_reg_t addr)
u8_t sys_read8(mm_reg_t addr)
{
uint8_t ret;
u8_t ret;
__asm__ volatile("movb %1, %0;\n\t"
: "=q"(ret)
: "m" (*(volatile uint8_t *) addr)
: "m" (*(volatile u8_t *) addr)
: "memory");
return ret;
}
static ALWAYS_INLINE
void sys_write16(uint16_t data, mm_reg_t addr)
void sys_write16(u16_t data, mm_reg_t addr)
{
__asm__ volatile("movw %0, %1;\n\t"
:
: "r"(data), "m" (*(volatile uint16_t *) addr)
: "r"(data), "m" (*(volatile u16_t *) addr)
: "memory");
}
static ALWAYS_INLINE
uint16_t sys_read16(mm_reg_t addr)
u16_t sys_read16(mm_reg_t addr)
{
uint16_t ret;
u16_t ret;
__asm__ volatile("movw %1, %0;\n\t"
: "=r"(ret)
: "m" (*(volatile uint16_t *) addr)
: "m" (*(volatile u16_t *) addr)
: "memory");
return ret;
}
static ALWAYS_INLINE
void sys_write32(uint32_t data, mm_reg_t addr)
void sys_write32(u32_t data, mm_reg_t addr)
{
__asm__ volatile("movl %0, %1;\n\t"
:
: "r"(data), "m" (*(volatile uint32_t *) addr)
: "r"(data), "m" (*(volatile u32_t *) addr)
: "memory");
}
static ALWAYS_INLINE
uint32_t sys_read32(mm_reg_t addr)
u32_t sys_read32(mm_reg_t addr)
{
uint32_t ret;
u32_t ret;
__asm__ volatile("movl %1, %0;\n\t"
: "=r"(ret)
: "m" (*(volatile uint32_t *) addr)
: "m" (*(volatile u32_t *) addr)
: "memory");
return ret;
@ -422,7 +422,7 @@ static ALWAYS_INLINE
void sys_set_bit(mem_addr_t addr, unsigned int bit)
{
__asm__ volatile("btsl %1, %0;\n\t"
: "+m" (*(volatile uint32_t *) (addr))
: "+m" (*(volatile u32_t *) (addr))
: "Ir" (bit)
: "memory");
}
@ -431,7 +431,7 @@ static ALWAYS_INLINE
void sys_clear_bit(mem_addr_t addr, unsigned int bit)
{
__asm__ volatile("btrl %1, %0;\n\t"
: "+m" (*(volatile uint32_t *) (addr))
: "+m" (*(volatile u32_t *) (addr))
: "Ir" (bit));
}
@ -442,7 +442,7 @@ static ALWAYS_INLINE
__asm__ volatile("btl %2, %1;\n\t"
"sbb %0, %0\n\t"
: "=r" (ret), "+m" (*(volatile uint32_t *) (addr))
: "=r" (ret), "+m" (*(volatile u32_t *) (addr))
: "Ir" (bit));
return ret;
@ -455,7 +455,7 @@ static ALWAYS_INLINE
__asm__ volatile("btsl %2, %1;\n\t"
"sbb %0, %0\n\t"
: "=r" (ret), "+m" (*(volatile uint32_t *) (addr))
: "=r" (ret), "+m" (*(volatile u32_t *) (addr))
: "Ir" (bit));
return ret;
@ -468,7 +468,7 @@ static ALWAYS_INLINE
__asm__ volatile("btrl %2, %1;\n\t"
"sbb %0, %0\n\t"
: "=r" (ret), "+m" (*(volatile uint32_t *) (addr))
: "=r" (ret), "+m" (*(volatile u32_t *) (addr))
: "Ir" (bit));
return ret;

2
include/arch/x86/irq_controller.h
View file

@ -63,7 +63,7 @@
* @returns: N/A
*/
static inline void _irq_controller_irq_config(unsigned int vector,
unsigned int irq, uint32_t flags)
unsigned int irq, u32_t flags)
{
__irq_controller_irq_config(vector, irq, flags);
}

176
include/arch/x86/segmentation.h
View file

@ -69,56 +69,56 @@ extern "C" {
/* Section 7.2.1 of IA architecture SW developer manual, Vol 3. */
struct __packed task_state_segment {
uint16_t backlink;
uint16_t reserved_1;
uint32_t esp0;
uint16_t ss0;
uint16_t reserved_2;
uint32_t esp1;
uint16_t ss1;
uint16_t reserved_3;
uint32_t esp2;
uint16_t ss2;
uint16_t reserved_4;
uint32_t cr3;
uint32_t eip;
uint32_t eflags;
uint32_t eax;
uint32_t ecx;
uint32_t edx;
uint32_t ebx;
uint32_t esp;
uint32_t ebp;
uint32_t esi;
uint32_t edi;
uint16_t es;
uint16_t reserved_5;
uint16_t cs;
uint16_t reserved_6;
uint16_t ss;
uint16_t reserved_7;
uint16_t ds;
uint16_t reserved_8;
uint16_t fs;
uint16_t reserved_9;
uint16_t gs;
uint16_t reserved_10;
uint16_t ldt_ss;
uint16_t reserved_11;
uint8_t t:1; /* Trap bit */
uint16_t reserved_12:15;
uint16_t iomap;
u16_t backlink;
u16_t reserved_1;
u32_t esp0;
u16_t ss0;
u16_t reserved_2;
u32_t esp1;
u16_t ss1;
u16_t reserved_3;
u32_t esp2;
u16_t ss2;
u16_t reserved_4;
u32_t cr3;
u32_t eip;
u32_t eflags;
u32_t eax;
u32_t ecx;
u32_t edx;
u32_t ebx;
u32_t esp;
u32_t ebp;
u32_t esi;
u32_t edi;
u16_t es;
u16_t reserved_5;
u16_t cs;
u16_t reserved_6;
u16_t ss;
u16_t reserved_7;
u16_t ds;
u16_t reserved_8;
u16_t fs;
u16_t reserved_9;
u16_t gs;
u16_t reserved_10;
u16_t ldt_ss;
u16_t reserved_11;
u8_t t:1; /* Trap bit */
u16_t reserved_12:15;
u16_t iomap;
};
/* Section 3.4.2 of IA architecture SW developer manual, Vol 3. */
struct __packed segment_selector {
union {
struct {
uint8_t rpl:2;
uint8_t table:1; /* 0=gdt 1=ldt */
uint16_t index:13;
u8_t rpl:2;
u8_t table:1; /* 0=gdt 1=ldt */
u16_t index:13;
};
uint16_t val;
u16_t val;
};
};
@ -138,39 +138,39 @@ struct __packed segment_descriptor {
/* First DWORD: 0-15 */
union {
/* IRQ, call, trap gates */
uint16_t limit_low;
u16_t limit_low;
/* Task gates */
uint16_t reserved_task_gate_0;
u16_t reserved_task_gate_0;
/* Everything else */
uint16_t offset_low;
u16_t offset_low;
};
/* First DWORD: 16-31 */
union {
/* Call/Task/Interrupt/Trap gates */
uint16_t segment_selector;
u16_t segment_selector;
/* TSS/LDT/Segments */
uint16_t base_low; /* Bits 0-15 */
u16_t base_low; /* Bits 0-15 */
};
/* Second DWORD: 0-7 */
union {
/* TSS/LDT/Segments */
uint8_t base_mid; /* Bits 16-23 */
u8_t base_mid; /* Bits 16-23 */
/* Task gates */
uint8_t reserved_task_gate_1;
u8_t reserved_task_gate_1;
/* IRQ/Trap/Call Gates */
struct {
/* Reserved except in case of call gates */
uint8_t reserved_or_param:5;
u8_t reserved_or_param:5;
/* Bits 5-7 0 0 0 per CPU manual */
uint8_t always_0_0:3;
u8_t always_0_0:3;
};
};
@ -179,59 +179,59 @@ struct __packed segment_descriptor {
/* Code or data Segments */
struct {
/* Set by the processor, init to 0 */
uint8_t accessed:1;
u8_t accessed:1;
/* executable ? readable : writable */
uint8_t rw:1;
u8_t rw:1;
/* executable ? conforming : direction */
uint8_t cd:1;
u8_t cd:1;
/* 1=code 0=data */
uint8_t executable:1;
u8_t executable:1;
/* Next 3 fields actually common to all */
/* 1=code or data, 0=system type */
uint8_t descriptor_type:1;
u8_t descriptor_type:1;
uint8_t dpl:2;
uint8_t present:1;
u8_t dpl:2;
u8_t present:1;
};
/* System types */
struct {
/* One of the SEG_TYPE_* macros above */
uint8_t type:4;
u8_t type:4;
/* Alas, C doesn't let you do a union of the first
* 4 bits of a bitfield and put the rest outside of it,
* it ends up getting padded.
*/
uint8_t use_other_union:4;
u8_t use_other_union:4;
};
};
/* Second DWORD: 16-31 */
union {
/* Call/IRQ/trap gates */
uint16_t offset_hi;
u16_t offset_hi;
/* Task Gates */
uint16_t reserved_task_gate_2;
u16_t reserved_task_gate_2;
/* segment/LDT/TSS */
struct {
uint8_t limit_hi:4;
u8_t limit_hi:4;
/* flags */
uint8_t avl:1; /* CPU ignores this */
u8_t avl:1; /* CPU ignores this */
/* 1=Indicates 64-bit code segment in IA-32e mode */
uint8_t flags_l:1; /* L field */
u8_t flags_l:1; /* L field */
uint8_t db:1; /* D/B field 1=32-bit 0=16-bit*/
uint8_t granularity:1;
u8_t db:1; /* D/B field 1=32-bit 0=16-bit*/
u8_t granularity:1;
uint8_t base_hi; /* Bits 24-31 */
u8_t base_hi; /* Bits 24-31 */
};
};
@ -242,7 +242,7 @@ struct __packed segment_descriptor {
* IA manual calls this a 'pseudo descriptor'.
*/
struct __packed pseudo_descriptor {
uint16_t size;
u16_t size;
struct segment_descriptor *entries;
};
@ -254,7 +254,7 @@ struct __packed far_ptr {
/** Far pointer offset, unused when invoking a task. */
void *offset;
/** Far pointer segment/gate selector. */
uint16_t sel;
u16_t sel;
};
@ -270,7 +270,7 @@ struct __packed far_ptr {
* or implement some tool to populate values post-link like gen_idt does.
*/
#define _LIMIT_AND_BASE(base_p, limit_p, granularity_p) \
.base_low = (((uint32_t)base_p) & 0xFFFF), \
.base_low = (((u32_t)base_p) & 0xFFFF), \
.base_mid = (((base_p) >> 16) & 0xFF), \
.base_hi = (((base_p) >> 24) & 0xFF), \
.limit_low = ((limit_p) & 0xFFFF), \
@ -399,8 +399,8 @@ extern struct pseudo_descriptor _gdt;
* @param segment_selector Segment selector
*/
static inline void _sd_set_seg_offset(struct segment_descriptor *sd,
uint16_t segment_selector,
uint32_t offset)
u16_t segment_selector,
u32_t offset)
{
sd->offset_low = offset & 0xFFFF;
sd->offset_hi = offset >> 16;
@ -418,8 +418,8 @@ static inline void _sd_set_seg_offset(struct segment_descriptor *sd,
* @param dpl descriptor privilege level
*/
static inline void _init_irq_gate(struct segment_descriptor *sd,
uint16_t seg_selector, uint32_t offset,
uint32_t dpl)
u16_t seg_selector, u32_t offset,
u32_t dpl)
{
_sd_set_seg_offset(sd, seg_selector, offset);
sd->dpl = dpl;
@ -434,7 +434,7 @@ static inline void _init_irq_gate(struct segment_descriptor *sd,
* @param sel Segment selector
* @param offset Offset within that selector
*/
static inline void _far_jump(uint16_t sel, void *offset)
static inline void _far_jump(u16_t sel, void *offset)
{
struct far_ptr ptr = {
.sel = sel,
@ -451,7 +451,7 @@ static inline void _far_jump(uint16_t sel, void *offset)
* @param sel Segment selector
* @param offset Offset within that selector
*/
static inline void _far_call(uint16_t sel, void *offset)
static inline void _far_call(u16_t sel, void *offset)
{
struct far_ptr ptr = {
.sel = sel,
@ -467,7 +467,7 @@ static inline void _far_call(uint16_t sel, void *offset)
*
* @param sel Segment selector in GDT for desired TSS
*/
static inline void _set_tss(uint16_t sel)
static inline void _set_tss(u16_t sel)
{
__asm__ __volatile__ ("ltr %0" :: "r" (sel));
}
@ -478,9 +478,9 @@ static inline void _set_tss(uint16_t sel)
*
* @return Segment selector for current IA task
*/
static inline uint16_t _get_tss(void)
static inline u16_t _get_tss(void)
{
uint16_t sel;
u16_t sel;
__asm__ __volatile__ ("str %0" : "=r" (sel));
return sel;
@ -514,9 +514,9 @@ static inline void _get_idt(struct pseudo_descriptor *idt)
*
* @return Segment selector in the GDT for the current LDT
*/
static inline uint16_t _get_ldt(void)
static inline u16_t _get_ldt(void)
{
uint16_t ret;
u16_t ret;
__asm__ __volatile__ ("sldt %0" : "=m" (ret));
return ret;
@ -528,7 +528,7 @@ static inline uint16_t _get_ldt(void)
*
* @param ldt Segment selector in the GDT for an LDT
*/
static inline void _set_ldt(uint16_t ldt)
static inline void _set_ldt(u16_t ldt)
{
__asm__ __volatile__ ("lldt %0" :: "m" (ldt));
@ -564,9 +564,9 @@ static inline void _set_idt(const struct pseudo_descriptor *idt)
*
* @return Segment selector
*/
static inline uint16_t _get_cs(void)
static inline u16_t _get_cs(void)
{
uint16_t cs = 0;
u16_t cs = 0;
__asm__ __volatile__ ("mov %%cs, %0" : "=r" (cs));
return cs;
@ -578,9 +578,9 @@ static inline uint16_t _get_cs(void)
*
* @return Segment selector
*/
static inline uint16_t _get_ds(void)
static inline u16_t _get_ds(void)
{
uint16_t ds = 0;
u16_t ds = 0;
__asm__ __volatile__ ("mov %%ds, %0" : "=r" (ds));
return ds;

10
include/arch/xtensa/arch.h
View file

@ -52,7 +52,7 @@ extern "C" {
#define _NANO_ERR_RESERVED_IRQ (4) /* Reserved interrupt */
/* Xtensa GPRs are often designated by two different names */
#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; }
#define sys_define_gpr_with_alias(name1, name2) union { u32_t name1, name2; }
#include <arch/xtensa/exc.h>
@ -68,7 +68,7 @@ extern "C" {
* @return most significant bit set, 0 if @a op is 0
*/
static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_msb_set(u32_t op)
{
if (!op)
return 0;
@ -87,13 +87,13 @@ static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
* @return least significant bit set, 0 if @a op is 0
*/
static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
static ALWAYS_INLINE unsigned int find_lsb_set(u32_t op)
{
return __builtin_ffs(op);
}
/* internal routine documented in C file, needed by IRQ_CONNECT() macro */
extern void _irq_priority_set(uint32_t irq, uint32_t prio, uint32_t flags);
extern void _irq_priority_set(u32_t irq, u32_t prio, u32_t flags);
/**
@ -142,7 +142,7 @@ extern void _irq_priority_set(uint32_t irq, uint32_t prio, uint32_t flags);
FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
const NANO_ESF *esf);
extern uint32_t _timer_cycle_get_32(void);
extern u32_t _timer_cycle_get_32(void);
#define _arch_k_cycle_get_32() _timer_cycle_get_32()
#endif /* !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__) */

2
include/arch/xtensa/exc.h
View file

@ -30,7 +30,7 @@ extern "C" {
struct __esf {
/* XXX - not finished yet */
sys_define_gpr_with_alias(a1, sp);
uint32_t pc;
u32_t pc;
};
typedef struct __esf NANO_ESF;

16
include/arch/xtensa/sys_io.h
View file

@ -12,15 +12,15 @@
/* Memory mapped registers I/O functions */
static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr)
static ALWAYS_INLINE u32_t sys_read32(mem_addr_t addr)
{
return *(volatile uint32_t *)addr;
return *(volatile u32_t *)addr;
}
static ALWAYS_INLINE void sys_write32(uint32_t data, mem_addr_t addr)
static ALWAYS_INLINE void sys_write32(u32_t data, mem_addr_t addr)
{
*(volatile uint32_t *)addr = data;
*(volatile u32_t *)addr = data;
}
@ -28,16 +28,16 @@ static ALWAYS_INLINE void sys_write32(uint32_t data, mem_addr_t addr)
static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit)
{
uint32_t temp = *(volatile uint32_t *)addr;
u32_t temp = *(volatile u32_t *)addr;
*(volatile uint32_t *)addr = temp | (1 << bit);
*(volatile u32_t *)addr = temp | (1 << bit);
}
static ALWAYS_INLINE void sys_clear_bit(mem_addr_t addr, unsigned int bit)
{
uint32_t temp = *(volatile uint32_t *)addr;
u32_t temp = *(volatile u32_t *)addr;
*(volatile uint32_t *)addr = temp & ~(1 << bit);
*(volatile u32_t *)addr = temp & ~(1 << bit);
}
static ALWAYS_INLINE int sys_test_bit(mem_addr_t addr, unsigned int bit)

4
include/arch/xtensa/xtensa_irq.h
View file

@ -19,7 +19,7 @@
*
* @return N/A
*/
static ALWAYS_INLINE void _arch_irq_enable(uint32_t irq)
static ALWAYS_INLINE void _arch_irq_enable(u32_t irq)
{
_xt_ints_on(1 << irq);
}
@ -33,7 +33,7 @@ static ALWAYS_INLINE void _arch_irq_enable(uint32_t irq)
*
* @return N/A
*/
static ALWAYS_INLINE void _arch_irq_disable(uint32_t irq)
static ALWAYS_INLINE void _arch_irq_disable(u32_t irq)
{
_xt_ints_off(1 << irq);
}