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xtensa: reset-vector.S hack for booting intel_s1000 [REVERTME]

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Setting CACHEATTR from _memmap_cacheattr_reset is making
the intel_s1000 SoC get into some unknown state. Removing
it for intel_s1000_crb for now.

Change-Id: Ib44638ef75de6200ef5c2aad55f093a633da864a
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Rajavardhan Gundi 2017-08-30 13:54:35 +05:30 • committed by Anas Nashif
commit c9ace83c89
1 changed files with 6 additions and 0 deletions
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6
arch/xtensa/core/startup/reset-vector.S
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@ -433,10 +433,16 @@ _xtos_mpu_attribs:
#elif XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR \ #elif XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR \
|| XCHAL_HAVE_XLT_CACHEATTR \ || XCHAL_HAVE_XLT_CACHEATTR \
|| (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY) || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
/* FixMe: Setting CACHEATTR from _memmap_cacheattr_reset is making the
* Intel_S1000 SoC get into some unknown state. Removing them only for
* Intel_S1000_CRB
*/
#ifndef CONFIG_BOARD_INTEL_S1000_CRB
/* note: absolute symbol, not a ptr */ /* note: absolute symbol, not a ptr */
movi a2, _memmap_cacheattr_reset movi a2, _memmap_cacheattr_reset
/* set CACHEATTR from a2 (clobbers a3-a8) */ /* set CACHEATTR from a2 (clobbers a3-a8) */
cacheattr_set cacheattr_set
#endif
#endif #endif
/* Now that caches are initialized, cache coherency can be enabled. */ /* Now that caches are initialized, cache coherency can be enabled. */