From c9ace83c896c2b8b047995762b8af9a2a9a9bdc2 Mon Sep 17 00:00:00 2001 From: Rajavardhan Gundi Date: Wed, 30 Aug 2017 13:54:35 +0530 Subject: [PATCH] xtensa: reset-vector.S hack for booting intel_s1000 [REVERTME] Setting CACHEATTR from _memmap_cacheattr_reset is making the intel_s1000 SoC get into some unknown state. Removing it for intel_s1000_crb for now. Change-Id: Ib44638ef75de6200ef5c2aad55f093a633da864a Signed-off-by: Rajavardhan Gundi Signed-off-by: Anas Nashif --- arch/xtensa/core/startup/reset-vector.S | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/xtensa/core/startup/reset-vector.S b/arch/xtensa/core/startup/reset-vector.S index 670e6b79815..49c861eddce 100644 --- a/arch/xtensa/core/startup/reset-vector.S +++ b/arch/xtensa/core/startup/reset-vector.S @@ -433,10 +433,16 @@ _xtos_mpu_attribs: #elif XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR \ || XCHAL_HAVE_XLT_CACHEATTR \ || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY) +/* FixMe: Setting CACHEATTR from _memmap_cacheattr_reset is making the + * Intel_S1000 SoC get into some unknown state. Removing them only for + * Intel_S1000_CRB + */ +#ifndef CONFIG_BOARD_INTEL_S1000_CRB /* note: absolute symbol, not a ptr */ movi a2, _memmap_cacheattr_reset /* set CACHEATTR from a2 (clobbers a3-a8) */ cacheattr_set +#endif #endif /* Now that caches are initialized, cache coherency can be enabled. */