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dts: esp32s3: add cache node to common dtsi

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Create the cache memory node instead of hardcoding addresses.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit is contained in:
Marek Matej 2025-02-10 14:52:45 +01:00 • committed by Benjamin Cabé
commit c9849c1d24
1 changed files with 12 additions and 0 deletions
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12
dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi
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@ -86,6 +86,18 @@
compatible = "simple-bus";
ranges;
icache0: memory@42000000 {
compatible = "zephyr,memory-region";
reg = <0x42000000 DT_SIZE_M(32)>;
zephyr,memory-region = "ICACHE";
};
dcache0: memory@3c000000 {
compatible = "zephyr,memory-region";
reg = <0x3c000000 DT_SIZE_M(32)>;
zephyr,memory-region = "DCACHE";
};
sram0: memory@40370000 {
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x40370000 DT_SIZE_K(32)>;