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soc/ite/ec: common: Modify the format to comply with check_compliance.py

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Modify the format to comply with check_compliance.py.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin 2024-10-22 18:40:54 +08:00 • committed by Benjamin Cabé
commit c7e6cfb8cb
2 changed files with 512 additions and 540 deletions
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23
soc/ite/ec/common/check_regs.c
View file

@ -165,30 +165,23 @@ IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_rx_connect_state, 0x0E);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_sof_timer_msb, 0x0F);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[0].ep_ctrl, 0x40);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[0].ep_status, 0x41);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
usb_ep_regs[EP0].ep_transtype_sts, 0x42);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
usb_ep_regs[EP0].ep_nak_transtype_sts, 0x43);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[EP0].ep_transtype_sts, 0x42);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[EP0].ep_nak_transtype_sts, 0x43);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[3].ep_ctrl, 0x4C);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[3].ep_status, 0x4D);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
usb_ep_regs[EP3].ep_transtype_sts, 0x4E);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
usb_ep_regs[EP3].ep_nak_transtype_sts, 0x4F);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[EP3].ep_transtype_sts, 0x4E);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[EP3].ep_nak_transtype_sts, 0x4F);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, dc_control, 0x50);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, dc_frame_num_lsp, 0x56);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[0].ep_rx_fifo_data, 0x60);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[0].ep_tx_fifo_ctrl, 0x74);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
fifo_regs[EP_EXT_REGS_9X].ext_4_15.epn0n1_ext_ctrl, 0x98);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
fifo_regs[EP_EXT_REGS_BX].fifo_ctrl.ep_fifo_ctrl, 0xB8);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
fifo_regs[EP_EXT_REGS_DX].ext_0_3.epn_ext_ctrl, 0xD6);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[EP_EXT_REGS_9X].ext_4_15.epn0n1_ext_ctrl,
0x98);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[EP_EXT_REGS_BX].fifo_ctrl.ep_fifo_ctrl, 0xB8);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[EP_EXT_REGS_DX].ext_0_3.epn_ext_ctrl, 0xD6);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_device_control, 0xE0);
IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, port1_misc_control, 0xE8);
/* KSCAN register structure check */
IT8XXX2_REG_SIZE_CHECK(kscan_it8xxx2_regs, 0x0F);
IT8XXX2_REG_OFFSET_CHECK(kscan_it8xxx2_regs, KBS_KSOL, 0x00);

45
soc/ite/ec/common/chip_chipregs.h
View file

@ -184,7 +184,6 @@
#endif
#define IVECT ECREG(EC_REG_BASE_ADDR + 0x3F10)
/*
* TODO: use pinctrl node instead of following register declarations
* to fix in tcpm\it83xx_pd.h.
@ -209,8 +208,8 @@
* the risk of unexpected compiling results.
*/
#define IT8XXX2_REG_SIZE_CHECK(reg_def, size) \
BUILD_ASSERT(sizeof(struct reg_def) == size, \
"Failed in size check of register structure!")
BUILD_ASSERT(sizeof(struct reg_def) == size, "Failed in size check of register " \
"structure!")
#define IT8XXX2_REG_OFFSET_CHECK(reg_def, member, offset) \
BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
"Failed in offset check of register structure member!")
@ -278,7 +277,6 @@ struct pwm_it8xxx2_regs {
#define IT8XXX2_PWM_T1DVS BIT(1)
#define IT8XXX2_PWM_T1CHSEL BIT(0)
/* --- Wake-Up Control (WUC) --- */
#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
#define IT8XXX2_WUC_BASE 0x00F01B00
@ -343,14 +341,12 @@ struct kscan_it8xxx2_regs {
/* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */
#define IT8XXX2_KBS_KSO2GOEN BIT(2)
/**
*
* (1Fxxh) External Timer & External Watchdog (ETWD)
*
*/
#define WDT_IT8XXX2_REGS_BASE \
((struct wdt_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(twd0)))
#define WDT_IT8XXX2_REGS_BASE ((struct wdt_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(twd0)))
#ifndef __ASSEMBLER__
struct wdt_it8xxx2_regs {
@ -409,9 +405,7 @@ struct wdt_it8xxx2_regs {
/* External Timer register fields */
/* External Timer 3~8 control */
#define IT8XXX2_EXT_ETX_COMB_RST_EN (IT8XXX2_EXT_ETXCOMB | \
IT8XXX2_EXT_ETXRST | \
IT8XXX2_EXT_ETXEN)
#define IT8XXX2_EXT_ETX_COMB_RST_EN (IT8XXX2_EXT_ETXCOMB | IT8XXX2_EXT_ETXRST | IT8XXX2_EXT_ETXEN)
#define IT8XXX2_EXT_ETXCOMB BIT(3)
#define IT8XXX2_EXT_ETXRST BIT(1)
#define IT8XXX2_EXT_ETXEN BIT(0)
@ -420,10 +414,8 @@ struct wdt_it8xxx2_regs {
#define IT8XXX2_EXT_TIMER_BASE DT_REG_ADDR(DT_NODELABEL(timer)) /*0x00F01F10*/
#define IT8XXX2_EXT_CTRLX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + (n << 3))
#define IT8XXX2_EXT_PSRX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + 0x01 + (n << 3))
#define IT8XXX2_EXT_CNTX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x04 + \
(n << 3))
#define IT8XXX2_EXT_CNTOX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x38 + \
(n << 2))
#define IT8XXX2_EXT_CNTX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x04 + (n << 3))
#define IT8XXX2_EXT_CNTOX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x38 + (n << 2))
/* Free run timer configurations */
#define FREE_RUN_TIMER EXT_TIMER_4
@ -454,7 +446,6 @@ enum ext_timer_idx {
};
#endif
/*
*
* (2Cxxh) Platform Environment Control Interface (PECI)
@ -660,7 +651,6 @@ struct ep_ext_regs_bx {
volatile uint8_t ep_ext_ctrl_bf;
};
/* From D6h to DDh are EP Extended Control Registers, and their
* definitions as follows:
* D6h: EP0_EXT_CTRL1
@ -707,7 +697,6 @@ struct ep_ext_regs_dx {
volatile uint8_t ep_ext_ctrl_df;
};
/* The USB EPx FIFO Registers Definitions
* EP0: 60h ~ 74h
* EP1: 80h ~ 94h
@ -740,12 +729,10 @@ struct it82xx2_usb_ep_fifo_regs {
struct ep_ext_regs_bx fifo_ctrl;
struct ep_ext_regs_dx ext_0_3;
};
};
/* USB Control registers */
#define USB_IT82XX2_REGS_BASE \
((struct usb_it82xx2_regs *)DT_REG_ADDR(DT_NODELABEL(usb0)))
#define USB_IT82XX2_REGS_BASE ((struct usb_it82xx2_regs *)DT_REG_ADDR(DT_NODELABEL(usb0)))
/* Bit definitions of the register Port0/Port1 MISC Control: 0XE4/0xE8 */
#define PULL_DOWN_EN BIT(4)
@ -873,7 +860,6 @@ struct usbpd_it8xxx2_regs {
#define IT8XXX2_USBPD_DISCONNECT_5_1K_CC1_DB BIT(2)
#define IT8XXX2_USBPD_DISCONNECT_POWER_CC1 BIT(1)
/**
*
* (10xxh) Shared Memory Flash Interface Bridge (SMFI) registers
@ -936,14 +922,12 @@ struct smfi_it8xxx2_regs {
/* Host RAM Window x Write Protect Enable (All protected) */
#define SMFI_HRAMWXWPE_ALL (BIT(5) | BIT(4))
/**
*
* (16xxh) General Purpose I/O Port (GPIO) registers
*
*/
#define GPIO_IT8XXX2_REG_BASE \
((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
#define GPIO_IT8XXX2_REG_BASE ((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
#ifndef __ASSEMBLER__
#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
@ -1129,9 +1113,8 @@ struct gpio_it8xxx2_regs {
* If both PULLUP and PULLDOWN are set to 1b, the corresponding port would be
* configured as tri-state.
*/
#define GPCR_PORT_PIN_MODE_TRISTATE (GPCR_PORT_PIN_MODE_INPUT | \
GPCR_PORT_PIN_MODE_PULLUP | \
GPCR_PORT_PIN_MODE_PULLDOWN)
#define GPCR_PORT_PIN_MODE_TRISTATE \
(GPCR_PORT_PIN_MODE_INPUT | GPCR_PORT_PIN_MODE_PULLUP | GPCR_PORT_PIN_MODE_PULLDOWN)
/* --- GPIO --- */
#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
@ -1164,7 +1147,6 @@ struct gpio_it8xxx2_regs {
#define IT8XXX2_GPIO_GPCRP0 ECREG(IT8XXX2_GPIO2_BASE + 0x18)
#define IT8XXX2_GPIO_GPCRP1 ECREG(IT8XXX2_GPIO2_BASE + 0x19)
/**
*
* (19xxh) Analog to Digital Converter (ADC) registers
@ -1544,8 +1526,7 @@ enum chip_pll_mode {
* (20xxh) General Control (GCTRL) registers
*
*/
#define GCTRL_IT8XXX2_REGS_BASE \
((struct gctrl_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gctrl)))
#define GCTRL_IT8XXX2_REGS_BASE ((struct gctrl_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gctrl)))
#ifndef __ASSEMBLER__
struct gctrl_it8xxx2_regs {
@ -1886,8 +1867,7 @@ struct kbc_regs {
#define KBC_KBHISR_IBF BIT(1)
/* A2 Address (A2) */
#define KBC_KBHISR_A2_ADDR BIT(3)
#define KBC_KBHISR_STS_MASK (KBC_KBHISR_OBF | KBC_KBHISR_IBF \
| KBC_KBHISR_A2_ADDR)
#define KBC_KBHISR_STS_MASK (KBC_KBHISR_OBF | KBC_KBHISR_IBF | KBC_KBHISR_A2_ADDR)
/* Clear Output Buffer Full */
#define KBC_KBHICR_COBF BIT(6)
@ -2184,7 +2164,6 @@ struct espi_queue1_regs {
#endif /* !__ASSEMBLER__ */
/**
*
* (3Axxh) SPI Slave Controller (SPISC) registers