From c7e6cfb8cb607cdb13c949afab8bc3b47ce0edb7 Mon Sep 17 00:00:00 2001 From: Tim Lin Date: Tue, 22 Oct 2024 18:40:54 +0800 Subject: [PATCH] soc/ite/ec: common: Modify the format to comply with check_compliance.py Modify the format to comply with check_compliance.py. Signed-off-by: Tim Lin --- soc/ite/ec/common/check_regs.c | 23 +- soc/ite/ec/common/chip_chipregs.h | 1029 ++++++++++++++--------------- 2 files changed, 512 insertions(+), 540 deletions(-) diff --git a/soc/ite/ec/common/check_regs.c b/soc/ite/ec/common/check_regs.c index 2fb6dcb4128..5c0a74891ce 100644 --- a/soc/ite/ec/common/check_regs.c +++ b/soc/ite/ec/common/check_regs.c @@ -165,30 +165,23 @@ IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_rx_connect_state, 0x0E); IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_sof_timer_msb, 0x0F); IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[0].ep_ctrl, 0x40); IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[0].ep_status, 0x41); -IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, - usb_ep_regs[EP0].ep_transtype_sts, 0x42); -IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, - usb_ep_regs[EP0].ep_nak_transtype_sts, 0x43); +IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[EP0].ep_transtype_sts, 0x42); +IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[EP0].ep_nak_transtype_sts, 0x43); IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[3].ep_ctrl, 0x4C); IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[3].ep_status, 0x4D); -IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, - usb_ep_regs[EP3].ep_transtype_sts, 0x4E); -IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, - usb_ep_regs[EP3].ep_nak_transtype_sts, 0x4F); +IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[EP3].ep_transtype_sts, 0x4E); +IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[EP3].ep_nak_transtype_sts, 0x4F); IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, dc_control, 0x50); IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, dc_frame_num_lsp, 0x56); IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[0].ep_rx_fifo_data, 0x60); IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[0].ep_tx_fifo_ctrl, 0x74); -IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, - fifo_regs[EP_EXT_REGS_9X].ext_4_15.epn0n1_ext_ctrl, 0x98); -IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, - fifo_regs[EP_EXT_REGS_BX].fifo_ctrl.ep_fifo_ctrl, 0xB8); -IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, - fifo_regs[EP_EXT_REGS_DX].ext_0_3.epn_ext_ctrl, 0xD6); +IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[EP_EXT_REGS_9X].ext_4_15.epn0n1_ext_ctrl, + 0x98); +IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[EP_EXT_REGS_BX].fifo_ctrl.ep_fifo_ctrl, 0xB8); +IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[EP_EXT_REGS_DX].ext_0_3.epn_ext_ctrl, 0xD6); IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_device_control, 0xE0); IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, port1_misc_control, 0xE8); - /* KSCAN register structure check */ IT8XXX2_REG_SIZE_CHECK(kscan_it8xxx2_regs, 0x0F); IT8XXX2_REG_OFFSET_CHECK(kscan_it8xxx2_regs, KBS_KSOL, 0x00); diff --git a/soc/ite/ec/common/chip_chipregs.h b/soc/ite/ec/common/chip_chipregs.h index 929f9bde9ae..3840df6261a 100644 --- a/soc/ite/ec/common/chip_chipregs.h +++ b/soc/ite/ec/common/chip_chipregs.h @@ -11,26 +11,26 @@ #define EC_REG_BASE_ADDR 0x00f00000 #ifdef _ASMLANGUAGE -#define ECREG(x) x +#define ECREG(x) x #else /* * Macros for hardware registers access. */ -#define ECREG(x) (*((volatile unsigned char *)(x))) -#define ECREG_u16(x) (*((volatile unsigned short *)(x))) -#define ECREG_u32(x) (*((volatile unsigned long *)(x))) +#define ECREG(x) (*((volatile unsigned char *)(x))) +#define ECREG_u16(x) (*((volatile unsigned short *)(x))) +#define ECREG_u32(x) (*((volatile unsigned long *)(x))) /* * MASK operation macros */ -#define SET_MASK(reg, bit_mask) ((reg) |= (bit_mask)) -#define CLEAR_MASK(reg, bit_mask) ((reg) &= (~(bit_mask))) -#define IS_MASK_SET(reg, bit_mask) (((reg) & (bit_mask)) != 0) +#define SET_MASK(reg, bit_mask) ((reg) |= (bit_mask)) +#define CLEAR_MASK(reg, bit_mask) ((reg) &= (~(bit_mask))) +#define IS_MASK_SET(reg, bit_mask) (((reg) & (bit_mask)) != 0) #endif /* _ASMLANGUAGE */ #ifndef REG_BASE_ADDR -#define REG_BASE_ADDR EC_REG_BASE_ADDR +#define REG_BASE_ADDR EC_REG_BASE_ADDR #endif /* Common definition */ @@ -39,41 +39,41 @@ * to api or calculate RPM) */ #ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ -#define EC_FREQ MHZ(24) +#define EC_FREQ MHZ(24) #else -#define EC_FREQ MHZ(8) +#define EC_FREQ MHZ(8) #endif /* --- General Control (GCTRL) --- */ -#define IT8XXX2_GCTRL_BASE 0x00F02000 -#define IT8XXX2_GCTRL_EIDSR ECREG(IT8XXX2_GCTRL_BASE + 0x31) -#define IT8XXX2_GCTRL_PMER3 ECREG(IT8XXX2_GCTRL_BASE + 0x46) +#define IT8XXX2_GCTRL_BASE 0x00F02000 +#define IT8XXX2_GCTRL_EIDSR ECREG(IT8XXX2_GCTRL_BASE + 0x31) +#define IT8XXX2_GCTRL_PMER3 ECREG(IT8XXX2_GCTRL_BASE + 0x46) /* RISC-V JTAG Debug Interface Enable */ -#define IT8XXX2_GCTRL_JTAGEN BIT(1) +#define IT8XXX2_GCTRL_JTAGEN BIT(1) /* RISC-V JTAG Debug Interface Selection */ -#define IT8XXX2_GCTRL_JTAGSEL BIT(0) -#define IT8XXX2_GCTRL_JTAG (IT8XXX2_GCTRL_JTAGEN | IT8XXX2_GCTRL_JTAGSEL) +#define IT8XXX2_GCTRL_JTAGSEL BIT(0) +#define IT8XXX2_GCTRL_JTAG (IT8XXX2_GCTRL_JTAGEN | IT8XXX2_GCTRL_JTAGSEL) #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2 -#define IT8XXX2_JTAG_PINS_BASE ECREG(0xF01660) -#define IT8XXX2_JTAG_VOLT_SET ECREG(0xF01648) +#define IT8XXX2_JTAG_PINS_BASE ECREG(0xF01660) +#define IT8XXX2_JTAG_VOLT_SET ECREG(0xF01648) #elif CONFIG_SOC_IT8XXX2_REG_SET_V1 -#define IT8XXX2_JTAG_PINS_BASE ECREG(0xF01610) -#define IT8XXX2_JTAG_VOLT_SET ECREG(0xF016e9) +#define IT8XXX2_JTAG_PINS_BASE ECREG(0xF01610) +#define IT8XXX2_JTAG_VOLT_SET ECREG(0xF016e9) #endif #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2 /* --- External GPIO Control (EGPIO) --- */ -#define IT8XXX2_EGPIO_BASE 0x00F02100 -#define IT8XXX2_EGPIO_EGCR ECREG(IT8XXX2_EGPIO_BASE + 0x04) +#define IT8XXX2_EGPIO_BASE 0x00F02100 +#define IT8XXX2_EGPIO_EGCR ECREG(IT8XXX2_EGPIO_BASE + 0x04) /* EGPIO register fields */ /* * 0x04: External GPIO Control * BIT(4): EXGPIO EGAD Pin Output Driving Disable */ -#define IT8XXX2_EGPIO_EEPODD BIT(4) +#define IT8XXX2_EGPIO_EEPODD BIT(4) #endif /** @@ -82,108 +82,107 @@ * */ #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1 -#define ISR0 ECREG(EC_REG_BASE_ADDR + 0x3F00) -#define ISR1 ECREG(EC_REG_BASE_ADDR + 0x3F01) -#define ISR2 ECREG(EC_REG_BASE_ADDR + 0x3F02) -#define ISR3 ECREG(EC_REG_BASE_ADDR + 0x3F03) -#define ISR4 ECREG(EC_REG_BASE_ADDR + 0x3F14) -#define ISR5 ECREG(EC_REG_BASE_ADDR + 0x3F18) -#define ISR6 ECREG(EC_REG_BASE_ADDR + 0x3F1C) -#define ISR7 ECREG(EC_REG_BASE_ADDR + 0x3F20) -#define ISR8 ECREG(EC_REG_BASE_ADDR + 0x3F24) -#define ISR9 ECREG(EC_REG_BASE_ADDR + 0x3F28) -#define ISR10 ECREG(EC_REG_BASE_ADDR + 0x3F2C) -#define ISR11 ECREG(EC_REG_BASE_ADDR + 0x3F30) -#define ISR12 ECREG(EC_REG_BASE_ADDR + 0x3F34) -#define ISR13 ECREG(EC_REG_BASE_ADDR + 0x3F38) -#define ISR14 ECREG(EC_REG_BASE_ADDR + 0x3F3C) -#define ISR15 ECREG(EC_REG_BASE_ADDR + 0x3F40) -#define ISR16 ECREG(EC_REG_BASE_ADDR + 0x3F44) -#define ISR17 ECREG(EC_REG_BASE_ADDR + 0x3F48) -#define ISR18 ECREG(EC_REG_BASE_ADDR + 0x3F4C) -#define ISR19 ECREG(EC_REG_BASE_ADDR + 0x3F50) -#define ISR20 ECREG(EC_REG_BASE_ADDR + 0x3F54) -#define ISR21 ECREG(EC_REG_BASE_ADDR + 0x3F58) -#define ISR22 ECREG(EC_REG_BASE_ADDR + 0x3F5C) -#define ISR23 ECREG(EC_REG_BASE_ADDR + 0x3F90) +#define ISR0 ECREG(EC_REG_BASE_ADDR + 0x3F00) +#define ISR1 ECREG(EC_REG_BASE_ADDR + 0x3F01) +#define ISR2 ECREG(EC_REG_BASE_ADDR + 0x3F02) +#define ISR3 ECREG(EC_REG_BASE_ADDR + 0x3F03) +#define ISR4 ECREG(EC_REG_BASE_ADDR + 0x3F14) +#define ISR5 ECREG(EC_REG_BASE_ADDR + 0x3F18) +#define ISR6 ECREG(EC_REG_BASE_ADDR + 0x3F1C) +#define ISR7 ECREG(EC_REG_BASE_ADDR + 0x3F20) +#define ISR8 ECREG(EC_REG_BASE_ADDR + 0x3F24) +#define ISR9 ECREG(EC_REG_BASE_ADDR + 0x3F28) +#define ISR10 ECREG(EC_REG_BASE_ADDR + 0x3F2C) +#define ISR11 ECREG(EC_REG_BASE_ADDR + 0x3F30) +#define ISR12 ECREG(EC_REG_BASE_ADDR + 0x3F34) +#define ISR13 ECREG(EC_REG_BASE_ADDR + 0x3F38) +#define ISR14 ECREG(EC_REG_BASE_ADDR + 0x3F3C) +#define ISR15 ECREG(EC_REG_BASE_ADDR + 0x3F40) +#define ISR16 ECREG(EC_REG_BASE_ADDR + 0x3F44) +#define ISR17 ECREG(EC_REG_BASE_ADDR + 0x3F48) +#define ISR18 ECREG(EC_REG_BASE_ADDR + 0x3F4C) +#define ISR19 ECREG(EC_REG_BASE_ADDR + 0x3F50) +#define ISR20 ECREG(EC_REG_BASE_ADDR + 0x3F54) +#define ISR21 ECREG(EC_REG_BASE_ADDR + 0x3F58) +#define ISR22 ECREG(EC_REG_BASE_ADDR + 0x3F5C) +#define ISR23 ECREG(EC_REG_BASE_ADDR + 0x3F90) -#define IER0 ECREG(EC_REG_BASE_ADDR + 0x3F04) -#define IER1 ECREG(EC_REG_BASE_ADDR + 0x3F05) -#define IER2 ECREG(EC_REG_BASE_ADDR + 0x3F06) -#define IER3 ECREG(EC_REG_BASE_ADDR + 0x3F07) -#define IER4 ECREG(EC_REG_BASE_ADDR + 0x3F15) -#define IER5 ECREG(EC_REG_BASE_ADDR + 0x3F19) -#define IER6 ECREG(EC_REG_BASE_ADDR + 0x3F1D) -#define IER7 ECREG(EC_REG_BASE_ADDR + 0x3F21) -#define IER8 ECREG(EC_REG_BASE_ADDR + 0x3F25) -#define IER9 ECREG(EC_REG_BASE_ADDR + 0x3F29) -#define IER10 ECREG(EC_REG_BASE_ADDR + 0x3F2D) -#define IER11 ECREG(EC_REG_BASE_ADDR + 0x3F31) -#define IER12 ECREG(EC_REG_BASE_ADDR + 0x3F35) -#define IER13 ECREG(EC_REG_BASE_ADDR + 0x3F39) -#define IER14 ECREG(EC_REG_BASE_ADDR + 0x3F3D) -#define IER15 ECREG(EC_REG_BASE_ADDR + 0x3F41) -#define IER16 ECREG(EC_REG_BASE_ADDR + 0x3F45) -#define IER17 ECREG(EC_REG_BASE_ADDR + 0x3F49) -#define IER18 ECREG(EC_REG_BASE_ADDR + 0x3F4D) -#define IER19 ECREG(EC_REG_BASE_ADDR + 0x3F51) -#define IER20 ECREG(EC_REG_BASE_ADDR + 0x3F55) -#define IER21 ECREG(EC_REG_BASE_ADDR + 0x3F59) -#define IER22 ECREG(EC_REG_BASE_ADDR + 0x3F5D) -#define IER23 ECREG(EC_REG_BASE_ADDR + 0x3F91) +#define IER0 ECREG(EC_REG_BASE_ADDR + 0x3F04) +#define IER1 ECREG(EC_REG_BASE_ADDR + 0x3F05) +#define IER2 ECREG(EC_REG_BASE_ADDR + 0x3F06) +#define IER3 ECREG(EC_REG_BASE_ADDR + 0x3F07) +#define IER4 ECREG(EC_REG_BASE_ADDR + 0x3F15) +#define IER5 ECREG(EC_REG_BASE_ADDR + 0x3F19) +#define IER6 ECREG(EC_REG_BASE_ADDR + 0x3F1D) +#define IER7 ECREG(EC_REG_BASE_ADDR + 0x3F21) +#define IER8 ECREG(EC_REG_BASE_ADDR + 0x3F25) +#define IER9 ECREG(EC_REG_BASE_ADDR + 0x3F29) +#define IER10 ECREG(EC_REG_BASE_ADDR + 0x3F2D) +#define IER11 ECREG(EC_REG_BASE_ADDR + 0x3F31) +#define IER12 ECREG(EC_REG_BASE_ADDR + 0x3F35) +#define IER13 ECREG(EC_REG_BASE_ADDR + 0x3F39) +#define IER14 ECREG(EC_REG_BASE_ADDR + 0x3F3D) +#define IER15 ECREG(EC_REG_BASE_ADDR + 0x3F41) +#define IER16 ECREG(EC_REG_BASE_ADDR + 0x3F45) +#define IER17 ECREG(EC_REG_BASE_ADDR + 0x3F49) +#define IER18 ECREG(EC_REG_BASE_ADDR + 0x3F4D) +#define IER19 ECREG(EC_REG_BASE_ADDR + 0x3F51) +#define IER20 ECREG(EC_REG_BASE_ADDR + 0x3F55) +#define IER21 ECREG(EC_REG_BASE_ADDR + 0x3F59) +#define IER22 ECREG(EC_REG_BASE_ADDR + 0x3F5D) +#define IER23 ECREG(EC_REG_BASE_ADDR + 0x3F91) -#define IELMR0 ECREG(EC_REG_BASE_ADDR + 0x3F08) -#define IELMR1 ECREG(EC_REG_BASE_ADDR + 0x3F09) -#define IELMR2 ECREG(EC_REG_BASE_ADDR + 0x3F0A) -#define IELMR3 ECREG(EC_REG_BASE_ADDR + 0x3F0B) -#define IELMR4 ECREG(EC_REG_BASE_ADDR + 0x3F16) -#define IELMR5 ECREG(EC_REG_BASE_ADDR + 0x3F1A) -#define IELMR6 ECREG(EC_REG_BASE_ADDR + 0x3F1E) -#define IELMR7 ECREG(EC_REG_BASE_ADDR + 0x3F22) -#define IELMR8 ECREG(EC_REG_BASE_ADDR + 0x3F26) -#define IELMR9 ECREG(EC_REG_BASE_ADDR + 0x3F2A) -#define IELMR10 ECREG(EC_REG_BASE_ADDR + 0x3F2E) -#define IELMR11 ECREG(EC_REG_BASE_ADDR + 0x3F32) -#define IELMR12 ECREG(EC_REG_BASE_ADDR + 0x3F36) -#define IELMR13 ECREG(EC_REG_BASE_ADDR + 0x3F3A) -#define IELMR14 ECREG(EC_REG_BASE_ADDR + 0x3F3E) -#define IELMR15 ECREG(EC_REG_BASE_ADDR + 0x3F42) -#define IELMR16 ECREG(EC_REG_BASE_ADDR + 0x3F46) -#define IELMR17 ECREG(EC_REG_BASE_ADDR + 0x3F4A) -#define IELMR18 ECREG(EC_REG_BASE_ADDR + 0x3F4E) -#define IELMR19 ECREG(EC_REG_BASE_ADDR + 0x3F52) -#define IELMR20 ECREG(EC_REG_BASE_ADDR + 0x3F56) -#define IELMR21 ECREG(EC_REG_BASE_ADDR + 0x3F5A) -#define IELMR22 ECREG(EC_REG_BASE_ADDR + 0x3F5E) -#define IELMR23 ECREG(EC_REG_BASE_ADDR + 0x3F92) +#define IELMR0 ECREG(EC_REG_BASE_ADDR + 0x3F08) +#define IELMR1 ECREG(EC_REG_BASE_ADDR + 0x3F09) +#define IELMR2 ECREG(EC_REG_BASE_ADDR + 0x3F0A) +#define IELMR3 ECREG(EC_REG_BASE_ADDR + 0x3F0B) +#define IELMR4 ECREG(EC_REG_BASE_ADDR + 0x3F16) +#define IELMR5 ECREG(EC_REG_BASE_ADDR + 0x3F1A) +#define IELMR6 ECREG(EC_REG_BASE_ADDR + 0x3F1E) +#define IELMR7 ECREG(EC_REG_BASE_ADDR + 0x3F22) +#define IELMR8 ECREG(EC_REG_BASE_ADDR + 0x3F26) +#define IELMR9 ECREG(EC_REG_BASE_ADDR + 0x3F2A) +#define IELMR10 ECREG(EC_REG_BASE_ADDR + 0x3F2E) +#define IELMR11 ECREG(EC_REG_BASE_ADDR + 0x3F32) +#define IELMR12 ECREG(EC_REG_BASE_ADDR + 0x3F36) +#define IELMR13 ECREG(EC_REG_BASE_ADDR + 0x3F3A) +#define IELMR14 ECREG(EC_REG_BASE_ADDR + 0x3F3E) +#define IELMR15 ECREG(EC_REG_BASE_ADDR + 0x3F42) +#define IELMR16 ECREG(EC_REG_BASE_ADDR + 0x3F46) +#define IELMR17 ECREG(EC_REG_BASE_ADDR + 0x3F4A) +#define IELMR18 ECREG(EC_REG_BASE_ADDR + 0x3F4E) +#define IELMR19 ECREG(EC_REG_BASE_ADDR + 0x3F52) +#define IELMR20 ECREG(EC_REG_BASE_ADDR + 0x3F56) +#define IELMR21 ECREG(EC_REG_BASE_ADDR + 0x3F5A) +#define IELMR22 ECREG(EC_REG_BASE_ADDR + 0x3F5E) +#define IELMR23 ECREG(EC_REG_BASE_ADDR + 0x3F92) -#define IPOLR0 ECREG(EC_REG_BASE_ADDR + 0x3F0C) -#define IPOLR1 ECREG(EC_REG_BASE_ADDR + 0x3F0D) -#define IPOLR2 ECREG(EC_REG_BASE_ADDR + 0x3F0E) -#define IPOLR3 ECREG(EC_REG_BASE_ADDR + 0x3F0F) -#define IPOLR4 ECREG(EC_REG_BASE_ADDR + 0x3F17) -#define IPOLR5 ECREG(EC_REG_BASE_ADDR + 0x3F1B) -#define IPOLR6 ECREG(EC_REG_BASE_ADDR + 0x3F1F) -#define IPOLR7 ECREG(EC_REG_BASE_ADDR + 0x3F23) -#define IPOLR8 ECREG(EC_REG_BASE_ADDR + 0x3F27) -#define IPOLR9 ECREG(EC_REG_BASE_ADDR + 0x3F2B) -#define IPOLR10 ECREG(EC_REG_BASE_ADDR + 0x3F2F) -#define IPOLR11 ECREG(EC_REG_BASE_ADDR + 0x3F33) -#define IPOLR12 ECREG(EC_REG_BASE_ADDR + 0x3F37) -#define IPOLR13 ECREG(EC_REG_BASE_ADDR + 0x3F3B) -#define IPOLR14 ECREG(EC_REG_BASE_ADDR + 0x3F3F) -#define IPOLR15 ECREG(EC_REG_BASE_ADDR + 0x3F43) -#define IPOLR16 ECREG(EC_REG_BASE_ADDR + 0x3F47) -#define IPOLR17 ECREG(EC_REG_BASE_ADDR + 0x3F4B) -#define IPOLR18 ECREG(EC_REG_BASE_ADDR + 0x3F4F) -#define IPOLR19 ECREG(EC_REG_BASE_ADDR + 0x3F53) -#define IPOLR20 ECREG(EC_REG_BASE_ADDR + 0x3F57) -#define IPOLR21 ECREG(EC_REG_BASE_ADDR + 0x3F5B) -#define IPOLR22 ECREG(EC_REG_BASE_ADDR + 0x3F5F) -#define IPOLR23 ECREG(EC_REG_BASE_ADDR + 0x3F93) +#define IPOLR0 ECREG(EC_REG_BASE_ADDR + 0x3F0C) +#define IPOLR1 ECREG(EC_REG_BASE_ADDR + 0x3F0D) +#define IPOLR2 ECREG(EC_REG_BASE_ADDR + 0x3F0E) +#define IPOLR3 ECREG(EC_REG_BASE_ADDR + 0x3F0F) +#define IPOLR4 ECREG(EC_REG_BASE_ADDR + 0x3F17) +#define IPOLR5 ECREG(EC_REG_BASE_ADDR + 0x3F1B) +#define IPOLR6 ECREG(EC_REG_BASE_ADDR + 0x3F1F) +#define IPOLR7 ECREG(EC_REG_BASE_ADDR + 0x3F23) +#define IPOLR8 ECREG(EC_REG_BASE_ADDR + 0x3F27) +#define IPOLR9 ECREG(EC_REG_BASE_ADDR + 0x3F2B) +#define IPOLR10 ECREG(EC_REG_BASE_ADDR + 0x3F2F) +#define IPOLR11 ECREG(EC_REG_BASE_ADDR + 0x3F33) +#define IPOLR12 ECREG(EC_REG_BASE_ADDR + 0x3F37) +#define IPOLR13 ECREG(EC_REG_BASE_ADDR + 0x3F3B) +#define IPOLR14 ECREG(EC_REG_BASE_ADDR + 0x3F3F) +#define IPOLR15 ECREG(EC_REG_BASE_ADDR + 0x3F43) +#define IPOLR16 ECREG(EC_REG_BASE_ADDR + 0x3F47) +#define IPOLR17 ECREG(EC_REG_BASE_ADDR + 0x3F4B) +#define IPOLR18 ECREG(EC_REG_BASE_ADDR + 0x3F4F) +#define IPOLR19 ECREG(EC_REG_BASE_ADDR + 0x3F53) +#define IPOLR20 ECREG(EC_REG_BASE_ADDR + 0x3F57) +#define IPOLR21 ECREG(EC_REG_BASE_ADDR + 0x3F5B) +#define IPOLR22 ECREG(EC_REG_BASE_ADDR + 0x3F5F) +#define IPOLR23 ECREG(EC_REG_BASE_ADDR + 0x3F93) #endif -#define IVECT ECREG(EC_REG_BASE_ADDR + 0x3F10) - +#define IVECT ECREG(EC_REG_BASE_ADDR + 0x3F10) /* * TODO: use pinctrl node instead of following register declarations @@ -191,29 +190,29 @@ */ /* GPIO control register */ #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1 -#define IT8XXX2_GPIO_GPCRB3 ECREG(EC_REG_BASE_ADDR + 0x161B) -#define IT8XXX2_GPIO_GPCRB4 ECREG(EC_REG_BASE_ADDR + 0x161C) -#define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x163C) -#define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x163D) -#define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1649) -#define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x164A) +#define IT8XXX2_GPIO_GPCRB3 ECREG(EC_REG_BASE_ADDR + 0x161B) +#define IT8XXX2_GPIO_GPCRB4 ECREG(EC_REG_BASE_ADDR + 0x161C) +#define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x163C) +#define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x163D) +#define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1649) +#define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x164A) #elif CONFIG_SOC_IT8XXX2_REG_SET_V2 -#define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x168C) -#define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x168D) -#define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1699) -#define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x169A) +#define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x168C) +#define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x168D) +#define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1699) +#define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x169A) #endif /* * IT8XXX2 register structure size/offset checking macro function to mitigate * the risk of unexpected compiling results. */ -#define IT8XXX2_REG_SIZE_CHECK(reg_def, size) \ - BUILD_ASSERT(sizeof(struct reg_def) == size, \ - "Failed in size check of register structure!") -#define IT8XXX2_REG_OFFSET_CHECK(reg_def, member, offset) \ - BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \ - "Failed in offset check of register structure member!") +#define IT8XXX2_REG_SIZE_CHECK(reg_def, size) \ + BUILD_ASSERT(sizeof(struct reg_def) == size, "Failed in size check of register " \ + "structure!") +#define IT8XXX2_REG_OFFSET_CHECK(reg_def, member, offset) \ + BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \ + "Failed in offset check of register structure member!") /** * @@ -271,23 +270,22 @@ struct pwm_it8xxx2_regs { /* PWM register fields */ /* 0x023: PWM Clock Control */ -#define IT8XXX2_PWM_PCCE BIT(1) +#define IT8XXX2_PWM_PCCE BIT(1) /* 0x048: Tachometer Switch Control */ -#define IT8XXX2_PWM_T0DVS BIT(3) -#define IT8XXX2_PWM_T0CHSEL BIT(2) -#define IT8XXX2_PWM_T1DVS BIT(1) -#define IT8XXX2_PWM_T1CHSEL BIT(0) - +#define IT8XXX2_PWM_T0DVS BIT(3) +#define IT8XXX2_PWM_T0CHSEL BIT(2) +#define IT8XXX2_PWM_T1DVS BIT(1) +#define IT8XXX2_PWM_T1CHSEL BIT(0) /* --- Wake-Up Control (WUC) --- */ #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1 -#define IT8XXX2_WUC_BASE 0x00F01B00 +#define IT8XXX2_WUC_BASE 0x00F01B00 /* TODO: should a defined interface for configuring wake-up interrupts */ -#define IT8XXX2_WUC_WUEMR1 (IT8XXX2_WUC_BASE + 0x00) -#define IT8XXX2_WUC_WUEMR5 (IT8XXX2_WUC_BASE + 0x0c) -#define IT8XXX2_WUC_WUESR1 (IT8XXX2_WUC_BASE + 0x04) -#define IT8XXX2_WUC_WUESR5 (IT8XXX2_WUC_BASE + 0x0d) +#define IT8XXX2_WUC_WUEMR1 (IT8XXX2_WUC_BASE + 0x00) +#define IT8XXX2_WUC_WUEMR5 (IT8XXX2_WUC_BASE + 0x0c) +#define IT8XXX2_WUC_WUESR1 (IT8XXX2_WUC_BASE + 0x04) +#define IT8XXX2_WUC_WUESR5 (IT8XXX2_WUC_BASE + 0x0d) #define IT8XXX2_WUC_WUBEMR1 (IT8XXX2_WUC_BASE + 0x3c) #define IT8XXX2_WUC_WUBEMR5 (IT8XXX2_WUC_BASE + 0x0f) #endif @@ -334,23 +332,21 @@ struct kscan_it8xxx2_regs { /* KBS register fields */ /* 0x002: Keyboard Scan Out Control */ -#define IT8XXX2_KBS_KSOPU BIT(2) -#define IT8XXX2_KBS_KSOOD BIT(0) +#define IT8XXX2_KBS_KSOPU BIT(2) +#define IT8XXX2_KBS_KSOOD BIT(0) /* 0x005: Keyboard Scan In Control */ -#define IT8XXX2_KBS_KSIPU BIT(2) +#define IT8XXX2_KBS_KSIPU BIT(2) /* 0x00D: Keyboard Scan Out [7:0] GPIO Control */ -#define IT8XXX2_KBS_KSO2GCTRL BIT(2) +#define IT8XXX2_KBS_KSO2GCTRL BIT(2) /* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */ -#define IT8XXX2_KBS_KSO2GOEN BIT(2) - +#define IT8XXX2_KBS_KSO2GOEN BIT(2) /** * * (1Fxxh) External Timer & External Watchdog (ETWD) * */ -#define WDT_IT8XXX2_REGS_BASE \ - ((struct wdt_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(twd0))) +#define WDT_IT8XXX2_REGS_BASE ((struct wdt_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(twd0))) #ifndef __ASSEMBLER__ struct wdt_it8xxx2_regs { @@ -389,49 +385,45 @@ struct wdt_it8xxx2_regs { /* WDT register fields */ /* 0x001: External Timer1/WDT Configuration */ -#define IT8XXX2_WDT_EWDKEYEN BIT(5) -#define IT8XXX2_WDT_EWDSRC BIT(4) -#define IT8XXX2_WDT_LEWDCNTL BIT(3) -#define IT8XXX2_WDT_LET1CNTL BIT(2) -#define IT8XXX2_WDT_LET1PS BIT(1) -#define IT8XXX2_WDT_LETWCFG BIT(0) +#define IT8XXX2_WDT_EWDKEYEN BIT(5) +#define IT8XXX2_WDT_EWDSRC BIT(4) +#define IT8XXX2_WDT_LEWDCNTL BIT(3) +#define IT8XXX2_WDT_LET1CNTL BIT(2) +#define IT8XXX2_WDT_LET1PS BIT(1) +#define IT8XXX2_WDT_LETWCFG BIT(0) /* 0x002: External Timer1 Prescaler */ -#define IT8XXX2_WDT_ETPS_32P768_KHZ 0x00 -#define IT8XXX2_WDT_ETPS_1P024_KHZ 0x01 -#define IT8XXX2_WDT_ETPS_32_HZ 0x02 +#define IT8XXX2_WDT_ETPS_32P768_KHZ 0x00 +#define IT8XXX2_WDT_ETPS_1P024_KHZ 0x01 +#define IT8XXX2_WDT_ETPS_32_HZ 0x02 /* 0x005: External Timer1/WDT Control */ -#define IT8XXX2_WDT_EWDSCEN BIT(5) -#define IT8XXX2_WDT_EWDSCMS BIT(4) -#define IT8XXX2_WDT_ET2TC BIT(3) -#define IT8XXX2_WDT_ET2RST BIT(2) -#define IT8XXX2_WDT_ET1TC BIT(1) -#define IT8XXX2_WDT_ET1RST BIT(0) +#define IT8XXX2_WDT_EWDSCEN BIT(5) +#define IT8XXX2_WDT_EWDSCMS BIT(4) +#define IT8XXX2_WDT_ET2TC BIT(3) +#define IT8XXX2_WDT_ET2RST BIT(2) +#define IT8XXX2_WDT_ET1TC BIT(1) +#define IT8XXX2_WDT_ET1RST BIT(0) /* External Timer register fields */ /* External Timer 3~8 control */ -#define IT8XXX2_EXT_ETX_COMB_RST_EN (IT8XXX2_EXT_ETXCOMB | \ - IT8XXX2_EXT_ETXRST | \ - IT8XXX2_EXT_ETXEN) -#define IT8XXX2_EXT_ETXCOMB BIT(3) -#define IT8XXX2_EXT_ETXRST BIT(1) -#define IT8XXX2_EXT_ETXEN BIT(0) +#define IT8XXX2_EXT_ETX_COMB_RST_EN (IT8XXX2_EXT_ETXCOMB | IT8XXX2_EXT_ETXRST | IT8XXX2_EXT_ETXEN) +#define IT8XXX2_EXT_ETXCOMB BIT(3) +#define IT8XXX2_EXT_ETXRST BIT(1) +#define IT8XXX2_EXT_ETXEN BIT(0) /* Control external timer3~8 */ -#define IT8XXX2_EXT_TIMER_BASE DT_REG_ADDR(DT_NODELABEL(timer)) /*0x00F01F10*/ -#define IT8XXX2_EXT_CTRLX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + (n << 3)) -#define IT8XXX2_EXT_PSRX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + 0x01 + (n << 3)) -#define IT8XXX2_EXT_CNTX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x04 + \ - (n << 3)) -#define IT8XXX2_EXT_CNTOX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x38 + \ - (n << 2)) +#define IT8XXX2_EXT_TIMER_BASE DT_REG_ADDR(DT_NODELABEL(timer)) /*0x00F01F10*/ +#define IT8XXX2_EXT_CTRLX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + (n << 3)) +#define IT8XXX2_EXT_PSRX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + 0x01 + (n << 3)) +#define IT8XXX2_EXT_CNTX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x04 + (n << 3)) +#define IT8XXX2_EXT_CNTOX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x38 + (n << 2)) /* Free run timer configurations */ -#define FREE_RUN_TIMER EXT_TIMER_4 -#define FREE_RUN_TIMER_IRQ DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, irq) +#define FREE_RUN_TIMER EXT_TIMER_4 +#define FREE_RUN_TIMER_IRQ DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, irq) /* Free run timer configurations */ -#define FREE_RUN_TIMER_FLAG DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, flags) +#define FREE_RUN_TIMER_FLAG DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, flags) /* Free run timer max count is 36.4 hr (base on clock source 32768Hz) */ -#define FREE_RUN_TIMER_MAX_CNT 0xFFFFFFFFUL +#define FREE_RUN_TIMER_MAX_CNT 0xFFFFFFFFUL #ifndef __ASSEMBLER__ enum ext_clk_src_sel { @@ -445,16 +437,15 @@ enum ext_clk_src_sel { * 32-bit timers: external timer 4, 6, and 8 */ enum ext_timer_idx { - EXT_TIMER_3 = 0, /* Event timer */ - EXT_TIMER_4, /* Free run timer */ - EXT_TIMER_5, /* Busy wait low timer */ - EXT_TIMER_6, /* Busy wait high timer */ + EXT_TIMER_3 = 0, /* Event timer */ + EXT_TIMER_4, /* Free run timer */ + EXT_TIMER_5, /* Busy wait low timer */ + EXT_TIMER_6, /* Busy wait high timer */ EXT_TIMER_7, EXT_TIMER_8, }; #endif - /* * * (2Cxxh) Platform Environment Control Interface (PECI) @@ -500,9 +491,9 @@ struct peci_it8xxx2_regs { * (2Fxxh) USB Device Controller (USBDC) Registers * */ -#define EP_EXT_REGS_9X 1 -#define EP_EXT_REGS_BX 2 -#define EP_EXT_REGS_DX 3 +#define EP_EXT_REGS_9X 1 +#define EP_EXT_REGS_BX 2 +#define EP_EXT_REGS_DX 3 #ifndef __ASSEMBLER__ @@ -660,7 +651,6 @@ struct ep_ext_regs_bx { volatile uint8_t ep_ext_ctrl_bf; }; - /* From D6h to DDh are EP Extended Control Registers, and their * definitions as follows: * D6h: EP0_EXT_CTRL1 @@ -707,7 +697,6 @@ struct ep_ext_regs_dx { volatile uint8_t ep_ext_ctrl_df; }; - /* The USB EPx FIFO Registers Definitions * EP0: 60h ~ 74h * EP1: 80h ~ 94h @@ -740,15 +729,13 @@ struct it82xx2_usb_ep_fifo_regs { struct ep_ext_regs_bx fifo_ctrl; struct ep_ext_regs_dx ext_0_3; }; - }; /* USB Control registers */ -#define USB_IT82XX2_REGS_BASE \ - ((struct usb_it82xx2_regs *)DT_REG_ADDR(DT_NODELABEL(usb0))) +#define USB_IT82XX2_REGS_BASE ((struct usb_it82xx2_regs *)DT_REG_ADDR(DT_NODELABEL(usb0))) /* Bit definitions of the register Port0/Port1 MISC Control: 0XE4/0xE8 */ -#define PULL_DOWN_EN BIT(4) +#define PULL_DOWN_EN BIT(4) struct usb_it82xx2_regs { /* 0x00: Host TX Contrl Register */ @@ -854,25 +841,24 @@ struct usbpd_it8xxx2_regs { /* USBPD controller register fields */ /* 0x004: CC General Configuration */ -#define IT8XXX2_USBPD_DISABLE_CC BIT(7) -#define IT8XXX2_USBPD_DISABLE_CC_VOL_DETECTOR BIT(6) -#define IT8XXX2_USBPD_CC_SELECT_RP_RESERVED (BIT(3) | BIT(2) | BIT(1)) -#define IT8XXX2_USBPD_CC_SELECT_RP_DEF (BIT(3) | BIT(2)) -#define IT8XXX2_USBPD_CC_SELECT_RP_1A5 BIT(3) -#define IT8XXX2_USBPD_CC_SELECT_RP_3A0 BIT(2) -#define IT8XXX2_USBPD_CC1_CC2_SELECTION BIT(0) +#define IT8XXX2_USBPD_DISABLE_CC BIT(7) +#define IT8XXX2_USBPD_DISABLE_CC_VOL_DETECTOR BIT(6) +#define IT8XXX2_USBPD_CC_SELECT_RP_RESERVED (BIT(3) | BIT(2) | BIT(1)) +#define IT8XXX2_USBPD_CC_SELECT_RP_DEF (BIT(3) | BIT(2)) +#define IT8XXX2_USBPD_CC_SELECT_RP_1A5 BIT(3) +#define IT8XXX2_USBPD_CC_SELECT_RP_3A0 BIT(2) +#define IT8XXX2_USBPD_CC1_CC2_SELECTION BIT(0) /* 0x005: CC Channel Setting */ -#define IT8XXX2_USBPD_CC2_DISCONNECT BIT(7) -#define IT8XXX2_USBPD_CC2_DISCONNECT_5_1K_TO_GND BIT(6) -#define IT8XXX2_USBPD_CC1_DISCONNECT BIT(3) -#define IT8XXX2_USBPD_CC1_DISCONNECT_5_1K_TO_GND BIT(2) -#define IT8XXX2_USBPD_CC1_CC2_RP_RD_SELECT (BIT(1) | BIT(5)) +#define IT8XXX2_USBPD_CC2_DISCONNECT BIT(7) +#define IT8XXX2_USBPD_CC2_DISCONNECT_5_1K_TO_GND BIT(6) +#define IT8XXX2_USBPD_CC1_DISCONNECT BIT(3) +#define IT8XXX2_USBPD_CC1_DISCONNECT_5_1K_TO_GND BIT(2) +#define IT8XXX2_USBPD_CC1_CC2_RP_RD_SELECT (BIT(1) | BIT(5)) /* 0x006: CC Pad Setting */ -#define IT8XXX2_USBPD_DISCONNECT_5_1K_CC2_DB BIT(6) -#define IT8XXX2_USBPD_DISCONNECT_POWER_CC2 BIT(5) -#define IT8XXX2_USBPD_DISCONNECT_5_1K_CC1_DB BIT(2) -#define IT8XXX2_USBPD_DISCONNECT_POWER_CC1 BIT(1) - +#define IT8XXX2_USBPD_DISCONNECT_5_1K_CC2_DB BIT(6) +#define IT8XXX2_USBPD_DISCONNECT_POWER_CC2 BIT(5) +#define IT8XXX2_USBPD_DISCONNECT_5_1K_CC1_DB BIT(2) +#define IT8XXX2_USBPD_DISCONNECT_POWER_CC1 BIT(1) /** * @@ -920,30 +906,28 @@ struct smfi_it8xxx2_regs { /* EC-Indirect read internal flash */ #define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6) /* Enable EC-indirect page program command */ -#define IT8XXX2_SMFI_MASK_ECINDPP BIT(3) +#define IT8XXX2_SMFI_MASK_ECINDPP BIT(3) /* Scratch SRAM 0 address(BIT(19)) */ -#define IT8XXX2_SMFI_SC0A19 BIT(7) +#define IT8XXX2_SMFI_SC0A19 BIT(7) /* Scratch SRAM enable */ -#define IT8XXX2_SMFI_SCAR0H_ENABLE BIT(3) +#define IT8XXX2_SMFI_SCAR0H_ENABLE BIT(3) /* H2RAM Path Select. 1b: H2RAM through LPC IO cycle. */ -#define SMFI_H2RAMPS BIT(4) +#define SMFI_H2RAMPS BIT(4) /* H2RAM Window 1 Enable */ -#define SMFI_H2RAMW1E BIT(1) +#define SMFI_H2RAMW1E BIT(1) /* H2RAM Window 0 Enable */ -#define SMFI_H2RAMW0E BIT(0) +#define SMFI_H2RAMW0E BIT(0) /* Host RAM Window x Write Protect Enable (All protected) */ -#define SMFI_HRAMWXWPE_ALL (BIT(5) | BIT(4)) - +#define SMFI_HRAMWXWPE_ALL (BIT(5) | BIT(4)) /** * * (16xxh) General Purpose I/O Port (GPIO) registers * */ -#define GPIO_IT8XXX2_REG_BASE \ - ((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr))) +#define GPIO_IT8XXX2_REG_BASE ((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr))) #ifndef __ASSEMBLER__ #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1 @@ -1095,30 +1079,30 @@ struct gpio_it8xxx2_regs { /* GPIO register fields */ /* 0x16: General Control 7 */ -#define IT8XXX2_GPIO_SMB2PS BIT(7) -#define IT8XXX2_GPIO_SMB3PS BIT(6) -#define IT8XXX2_GPIO_SMB5PS BIT(5) +#define IT8XXX2_GPIO_SMB2PS BIT(7) +#define IT8XXX2_GPIO_SMB3PS BIT(6) +#define IT8XXX2_GPIO_SMB5PS BIT(5) #endif #endif /* !__ASSEMBLER__ */ /* GPIO register fields */ /* 0x00: General Control */ -#define IT8XXX2_GPIO_LPCRSTEN (BIT(2) | BIT(1)) -#define IT8XXX2_GPIO_GCR_ESPI_RST_D2 0x2 -#define IT8XXX2_GPIO_GCR_ESPI_RST_POS 1 -#define IT8XXX2_GPIO_GCR_ESPI_RST_EN_MASK (0x3 << IT8XXX2_GPIO_GCR_ESPI_RST_POS) +#define IT8XXX2_GPIO_LPCRSTEN (BIT(2) | BIT(1)) +#define IT8XXX2_GPIO_GCR_ESPI_RST_D2 0x2 +#define IT8XXX2_GPIO_GCR_ESPI_RST_POS 1 +#define IT8XXX2_GPIO_GCR_ESPI_RST_EN_MASK (0x3 << IT8XXX2_GPIO_GCR_ESPI_RST_POS) /* 0xF0: General Control 1 */ -#define IT8XXX2_GPIO_U2CTRL_SIN1_SOUT1_EN BIT(2) -#define IT8XXX2_GPIO_U1CTRL_SIN0_SOUT0_EN BIT(0) +#define IT8XXX2_GPIO_U2CTRL_SIN1_SOUT1_EN BIT(2) +#define IT8XXX2_GPIO_U1CTRL_SIN0_SOUT0_EN BIT(0) /* 0xE6: General Control 21 */ -#define IT8XXX2_GPIO_GPH1VS BIT(1) -#define IT8XXX2_GPIO_GPH2VS BIT(0) +#define IT8XXX2_GPIO_GPH1VS BIT(1) +#define IT8XXX2_GPIO_GPH2VS BIT(0) -#define KSIX_KSOX_KBS_GPIO_MODE BIT(7) -#define KSIX_KSOX_GPIO_OUTPUT BIT(6) -#define KSIX_KSOX_GPIO_PULLUP BIT(2) -#define KSIX_KSOX_GPIO_PULLDOWN BIT(1) +#define KSIX_KSOX_KBS_GPIO_MODE BIT(7) +#define KSIX_KSOX_GPIO_OUTPUT BIT(6) +#define KSIX_KSOX_GPIO_PULLUP BIT(2) +#define KSIX_KSOX_GPIO_PULLDOWN BIT(1) #define GPCR_PORT_PIN_MODE_INPUT BIT(7) #define GPCR_PORT_PIN_MODE_OUTPUT BIT(6) @@ -1129,13 +1113,12 @@ struct gpio_it8xxx2_regs { * If both PULLUP and PULLDOWN are set to 1b, the corresponding port would be * configured as tri-state. */ -#define GPCR_PORT_PIN_MODE_TRISTATE (GPCR_PORT_PIN_MODE_INPUT | \ - GPCR_PORT_PIN_MODE_PULLUP | \ - GPCR_PORT_PIN_MODE_PULLDOWN) +#define GPCR_PORT_PIN_MODE_TRISTATE \ + (GPCR_PORT_PIN_MODE_INPUT | GPCR_PORT_PIN_MODE_PULLUP | GPCR_PORT_PIN_MODE_PULLDOWN) /* --- GPIO --- */ #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1 -#define IT8XXX2_GPIO_BASE 0x00F01600 +#define IT8XXX2_GPIO_BASE 0x00F01600 #define IT8XXX2_GPIO_GCRX(offset) ECREG(IT8XXX2_GPIO_BASE + (offset)) #define IT8XXX2_GPIO_GCR25_OFFSET 0xd1 @@ -1161,9 +1144,8 @@ struct gpio_it8xxx2_regs { */ #define IT8XXX2_GPIO2_BASE 0x00F03E00 -#define IT8XXX2_GPIO_GPCRP0 ECREG(IT8XXX2_GPIO2_BASE + 0x18) -#define IT8XXX2_GPIO_GPCRP1 ECREG(IT8XXX2_GPIO2_BASE + 0x19) - +#define IT8XXX2_GPIO_GPCRP0 ECREG(IT8XXX2_GPIO2_BASE + 0x18) +#define IT8XXX2_GPIO_GPCRP1 ECREG(IT8XXX2_GPIO2_BASE + 0x19) /** * @@ -1227,38 +1209,38 @@ struct adc_it8xxx2_regs { #endif /* !__ASSEMBLER__ */ /* ADC conversion time select 1 */ -#define IT8XXX2_ADC_ADCCTS1 BIT(7) +#define IT8XXX2_ADC_ADCCTS1 BIT(7) /* Analog accuracy initialization */ -#define IT8XXX2_ADC_AINITB BIT(3) +#define IT8XXX2_ADC_AINITB BIT(3) /* ADC conversion time select 0 */ -#define IT8XXX2_ADC_ADCCTS0 BIT(5) +#define IT8XXX2_ADC_ADCCTS0 BIT(5) /* ADC module enable */ -#define IT8XXX2_ADC_ADCEN BIT(0) +#define IT8XXX2_ADC_ADCEN BIT(0) /* ADC data buffer keep enable */ -#define IT8XXX2_ADC_DBKEN BIT(7) +#define IT8XXX2_ADC_DBKEN BIT(7) /* W/C data valid flag */ -#define IT8XXX2_ADC_DATVAL BIT(7) +#define IT8XXX2_ADC_DATVAL BIT(7) /* Data valid interrupt of adc */ -#define IT8XXX2_ADC_INTDVEN BIT(5) +#define IT8XXX2_ADC_INTDVEN BIT(5) /* Voltage channel enable (Channel 4~7 and 13~16) */ -#define IT8XXX2_ADC_VCHEN BIT(4) +#define IT8XXX2_ADC_VCHEN BIT(4) /* Automatic hardware calibration enable */ -#define IT8XXX2_ADC_AHCE BIT(7) +#define IT8XXX2_ADC_AHCE BIT(7) /* 0x046, 0x049, 0x04c, 0x06e, 0x071, 0x074: Voltage comparator x control */ -#define IT8XXX2_VCMP_CMPEN BIT(7) -#define IT8XXX2_VCMP_CMPINTEN BIT(6) -#define IT8XXX2_VCMP_GREATER_THRESHOLD BIT(5) -#define IT8XXX2_VCMP_EDGE_TRIGGER BIT(4) -#define IT8XXX2_VCMP_GPIO_ACTIVE_LOW BIT(3) +#define IT8XXX2_VCMP_CMPEN BIT(7) +#define IT8XXX2_VCMP_CMPINTEN BIT(6) +#define IT8XXX2_VCMP_GREATER_THRESHOLD BIT(5) +#define IT8XXX2_VCMP_EDGE_TRIGGER BIT(4) +#define IT8XXX2_VCMP_GPIO_ACTIVE_LOW BIT(3) /* 0x077~0x07c: Voltage comparator x channel select MSB */ -#define IT8XXX2_VCMP_VCMPXCSELM BIT(0) +#define IT8XXX2_VCMP_VCMPXCSELM BIT(0) /** * * (1Exxh) Clock and Power Management (ECPM) registers * */ -#define IT8XXX2_ECPM_BASE 0x00F01E00 +#define IT8XXX2_ECPM_BASE 0x00F01E00 #ifndef __ASSEMBLER__ enum chip_pll_mode { @@ -1271,80 +1253,80 @@ enum chip_pll_mode { * TODO: use ecpm_it8xxx2_regs instead of following register declarations * to fix in soc.c. */ -#define IT8XXX2_ECPM_PLLCTRL ECREG(IT8XXX2_ECPM_BASE + 0x03) -#define IT8XXX2_ECPM_AUTOCG ECREG(IT8XXX2_ECPM_BASE + 0x04) -#define IT8XXX2_ECPM_CGCTRL3R ECREG(IT8XXX2_ECPM_BASE + 0x05) -#define IT8XXX2_ECPM_PLLFREQR ECREG(IT8XXX2_ECPM_BASE + 0x06) -#define IT8XXX2_ECPM_PLLCSS ECREG(IT8XXX2_ECPM_BASE + 0x08) -#define IT8XXX2_ECPM_SCDCR0 ECREG(IT8XXX2_ECPM_BASE + 0x0c) -#define IT8XXX2_ECPM_SCDCR1 ECREG(IT8XXX2_ECPM_BASE + 0x0d) -#define IT8XXX2_ECPM_SCDCR2 ECREG(IT8XXX2_ECPM_BASE + 0x0e) -#define IT8XXX2_ECPM_SCDCR3 ECREG(IT8XXX2_ECPM_BASE + 0x0f) -#define IT8XXX2_ECPM_SCDCR4 ECREG(IT8XXX2_ECPM_BASE + 0x10) -#define IT8XXX2_ECPM_PFACC0R ECREG(IT8XXX2_ECPM_BASE + 0x20) -#define IT8XXX2_ECPM_PFACC1R ECREG(IT8XXX2_ECPM_BASE + 0x21) -#define IT8XXX2_ECPM_PFACC2R ECREG(IT8XXX2_ECPM_BASE + 0x40) -#define IT8XXX2_ECPM_LCOTF2 ECREG(IT8XXX2_ECPM_BASE + 0x54) -#define IT8XXX2_ECPM_LCOCR ECREG(IT8XXX2_ECPM_BASE + 0x55) -#define IT8XXX2_ECPM_LCOCR1 ECREG(IT8XXX2_ECPM_BASE + 0x57) +#define IT8XXX2_ECPM_PLLCTRL ECREG(IT8XXX2_ECPM_BASE + 0x03) +#define IT8XXX2_ECPM_AUTOCG ECREG(IT8XXX2_ECPM_BASE + 0x04) +#define IT8XXX2_ECPM_CGCTRL3R ECREG(IT8XXX2_ECPM_BASE + 0x05) +#define IT8XXX2_ECPM_PLLFREQR ECREG(IT8XXX2_ECPM_BASE + 0x06) +#define IT8XXX2_ECPM_PLLCSS ECREG(IT8XXX2_ECPM_BASE + 0x08) +#define IT8XXX2_ECPM_SCDCR0 ECREG(IT8XXX2_ECPM_BASE + 0x0c) +#define IT8XXX2_ECPM_SCDCR1 ECREG(IT8XXX2_ECPM_BASE + 0x0d) +#define IT8XXX2_ECPM_SCDCR2 ECREG(IT8XXX2_ECPM_BASE + 0x0e) +#define IT8XXX2_ECPM_SCDCR3 ECREG(IT8XXX2_ECPM_BASE + 0x0f) +#define IT8XXX2_ECPM_SCDCR4 ECREG(IT8XXX2_ECPM_BASE + 0x10) +#define IT8XXX2_ECPM_PFACC0R ECREG(IT8XXX2_ECPM_BASE + 0x20) +#define IT8XXX2_ECPM_PFACC1R ECREG(IT8XXX2_ECPM_BASE + 0x21) +#define IT8XXX2_ECPM_PFACC2R ECREG(IT8XXX2_ECPM_BASE + 0x40) +#define IT8XXX2_ECPM_LCOTF2 ECREG(IT8XXX2_ECPM_BASE + 0x54) +#define IT8XXX2_ECPM_LCOCR ECREG(IT8XXX2_ECPM_BASE + 0x55) +#define IT8XXX2_ECPM_LCOCR1 ECREG(IT8XXX2_ECPM_BASE + 0x57) /* * The count number of the counter for 25 ms register. * The 25 ms register is calculated by (count number *1.024 kHz). */ -#define I2C_CLK_LOW_TIMEOUT 255 /* ~=249 ms */ +#define I2C_CLK_LOW_TIMEOUT 255 /* ~=249 ms */ /** * * (1Cxxh) SMBus Interface (SMB) registers * */ -#define IT8XXX2_SMB_BASE 0x00F01C00 +#define IT8XXX2_SMB_BASE 0x00F01C00 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1 -#define IT8XXX2_SMB_4P7USL ECREG(IT8XXX2_SMB_BASE + 0x00) -#define IT8XXX2_SMB_4P0USL ECREG(IT8XXX2_SMB_BASE + 0x01) -#define IT8XXX2_SMB_300NS ECREG(IT8XXX2_SMB_BASE + 0x02) -#define IT8XXX2_SMB_250NS ECREG(IT8XXX2_SMB_BASE + 0x03) -#define IT8XXX2_SMB_25MS ECREG(IT8XXX2_SMB_BASE + 0x04) -#define IT8XXX2_SMB_45P3USL ECREG(IT8XXX2_SMB_BASE + 0x05) -#define IT8XXX2_SMB_45P3USH ECREG(IT8XXX2_SMB_BASE + 0x06) -#define IT8XXX2_SMB_4P7A4P0H ECREG(IT8XXX2_SMB_BASE + 0x07) -#define IT8XXX2_SMB_SLVISELR ECREG(IT8XXX2_SMB_BASE + 0x08) -#define IT8XXX2_SMB_SCLKTS(ch) ECREG(IT8XXX2_SMB_BASE + 0x09 + ch) -#define IT8XXX2_SMB_MSTFCTRL1 ECREG(IT8XXX2_SMB_BASE + 0x0D) -#define IT8XXX2_SMB_MSTFSTS1 ECREG(IT8XXX2_SMB_BASE + 0x0E) -#define IT8XXX2_SMB_MSTFCTRL2 ECREG(IT8XXX2_SMB_BASE + 0x0F) -#define IT8XXX2_SMB_MSTFSTS2 ECREG(IT8XXX2_SMB_BASE + 0x10) -#define IT8XXX2_SMB_SMB45CHS ECREG(IT8XXX2_SMB_BASE + 0x11) -#define IT8XXX2_SMB_I2CW2RF ECREG(IT8XXX2_SMB_BASE + 0x12) -#define IT8XXX2_SMB_IWRFISTA ECREG(IT8XXX2_SMB_BASE + 0x13) -#define IT8XXX2_SMB_SMB01CHS ECREG(IT8XXX2_SMB_BASE + 0x20) -#define IT8XXX2_SMB_SMB23CHS ECREG(IT8XXX2_SMB_BASE + 0x21) -#define IT8XXX2_SMB_SFFCTL ECREG(IT8XXX2_SMB_BASE + 0x55) -#define IT8XXX2_SMB_HOSTA(base) ECREG(base + 0x00) -#define IT8XXX2_SMB_HOCTL(base) ECREG(base + 0x01) -#define IT8XXX2_SMB_HOCMD(base) ECREG(base + 0x02) -#define IT8XXX2_SMB_TRASLA(base) ECREG(base + 0x03) -#define IT8XXX2_SMB_D0REG(base) ECREG(base + 0x04) -#define IT8XXX2_SMB_D1REG(base) ECREG(base + 0x05) -#define IT8XXX2_SMB_HOBDB(base) ECREG(base + 0x06) -#define IT8XXX2_SMB_PECERC(base) ECREG(base + 0x07) -#define IT8XXX2_SMB_SMBPCTL(base) ECREG(base + 0x0A) -#define IT8XXX2_SMB_HOCTL2(base) ECREG(base + 0x10) +#define IT8XXX2_SMB_4P7USL ECREG(IT8XXX2_SMB_BASE + 0x00) +#define IT8XXX2_SMB_4P0USL ECREG(IT8XXX2_SMB_BASE + 0x01) +#define IT8XXX2_SMB_300NS ECREG(IT8XXX2_SMB_BASE + 0x02) +#define IT8XXX2_SMB_250NS ECREG(IT8XXX2_SMB_BASE + 0x03) +#define IT8XXX2_SMB_25MS ECREG(IT8XXX2_SMB_BASE + 0x04) +#define IT8XXX2_SMB_45P3USL ECREG(IT8XXX2_SMB_BASE + 0x05) +#define IT8XXX2_SMB_45P3USH ECREG(IT8XXX2_SMB_BASE + 0x06) +#define IT8XXX2_SMB_4P7A4P0H ECREG(IT8XXX2_SMB_BASE + 0x07) +#define IT8XXX2_SMB_SLVISELR ECREG(IT8XXX2_SMB_BASE + 0x08) +#define IT8XXX2_SMB_SCLKTS(ch) ECREG(IT8XXX2_SMB_BASE + 0x09 + ch) +#define IT8XXX2_SMB_MSTFCTRL1 ECREG(IT8XXX2_SMB_BASE + 0x0D) +#define IT8XXX2_SMB_MSTFSTS1 ECREG(IT8XXX2_SMB_BASE + 0x0E) +#define IT8XXX2_SMB_MSTFCTRL2 ECREG(IT8XXX2_SMB_BASE + 0x0F) +#define IT8XXX2_SMB_MSTFSTS2 ECREG(IT8XXX2_SMB_BASE + 0x10) +#define IT8XXX2_SMB_SMB45CHS ECREG(IT8XXX2_SMB_BASE + 0x11) +#define IT8XXX2_SMB_I2CW2RF ECREG(IT8XXX2_SMB_BASE + 0x12) +#define IT8XXX2_SMB_IWRFISTA ECREG(IT8XXX2_SMB_BASE + 0x13) +#define IT8XXX2_SMB_SMB01CHS ECREG(IT8XXX2_SMB_BASE + 0x20) +#define IT8XXX2_SMB_SMB23CHS ECREG(IT8XXX2_SMB_BASE + 0x21) +#define IT8XXX2_SMB_SFFCTL ECREG(IT8XXX2_SMB_BASE + 0x55) +#define IT8XXX2_SMB_HOSTA(base) ECREG(base + 0x00) +#define IT8XXX2_SMB_HOCTL(base) ECREG(base + 0x01) +#define IT8XXX2_SMB_HOCMD(base) ECREG(base + 0x02) +#define IT8XXX2_SMB_TRASLA(base) ECREG(base + 0x03) +#define IT8XXX2_SMB_D0REG(base) ECREG(base + 0x04) +#define IT8XXX2_SMB_D1REG(base) ECREG(base + 0x05) +#define IT8XXX2_SMB_HOBDB(base) ECREG(base + 0x06) +#define IT8XXX2_SMB_PECERC(base) ECREG(base + 0x07) +#define IT8XXX2_SMB_SMBPCTL(base) ECREG(base + 0x0A) +#define IT8XXX2_SMB_HOCTL2(base) ECREG(base + 0x10) #elif CONFIG_SOC_IT8XXX2_REG_SET_V2 -#define IT8XXX2_SMB_SLVISEL ECREG(IT8XXX2_SMB_BASE + 0x08) -#define IT8XXX2_SMB_SMB01CHS ECREG(IT8XXX2_SMB_BASE + 0x09) -#define IT8XXX2_SMB_SMB23CHS ECREG(IT8XXX2_SMB_BASE + 0x0A) -#define IT8XXX2_SMB_SMB45CHS ECREG(IT8XXX2_SMB_BASE + 0x0B) -#define IT8XXX2_SMB_SCLKTS_BRGS ECREG(IT8XXX2_SMB_BASE + 0x80) -#define IT8XXX2_SMB_SCLKTS_BRGM ECREG(IT8XXX2_SMB_BASE + 0x81) -#define IT8XXX2_SMB_CHSBRG ECREG(IT8XXX2_SMB_BASE + 0x82) -#define IT8XXX2_SMB_CHSMOT ECREG(IT8XXX2_SMB_BASE + 0x83) +#define IT8XXX2_SMB_SLVISEL ECREG(IT8XXX2_SMB_BASE + 0x08) +#define IT8XXX2_SMB_SMB01CHS ECREG(IT8XXX2_SMB_BASE + 0x09) +#define IT8XXX2_SMB_SMB23CHS ECREG(IT8XXX2_SMB_BASE + 0x0A) +#define IT8XXX2_SMB_SMB45CHS ECREG(IT8XXX2_SMB_BASE + 0x0B) +#define IT8XXX2_SMB_SCLKTS_BRGS ECREG(IT8XXX2_SMB_BASE + 0x80) +#define IT8XXX2_SMB_SCLKTS_BRGM ECREG(IT8XXX2_SMB_BASE + 0x81) +#define IT8XXX2_SMB_CHSBRG ECREG(IT8XXX2_SMB_BASE + 0x82) +#define IT8XXX2_SMB_CHSMOT ECREG(IT8XXX2_SMB_BASE + 0x83) /* SMBus register fields */ /* 0x80: SMCLK Timing Setting Register Bridge Slave */ -#define IT8XXX2_SMB_PREDEN BIT(7) +#define IT8XXX2_SMB_PREDEN BIT(7) #endif /** @@ -1352,125 +1334,125 @@ enum chip_pll_mode { * Ch_D: 0x00F03680, Ch_E: 0x00F03500, Ch_F: 0x00F03580 * Ch_D: ch = 0x03, Ch_E: ch = 0x00, Ch_F: ch = 0x01 */ -#define IT8XXX2_I2C_DRR(base) ECREG(base + 0x00) -#define IT8XXX2_I2C_PSR(base) ECREG(base + 0x01) -#define IT8XXX2_I2C_HSPR(base) ECREG(base + 0x02) -#define IT8XXX2_I2C_STR(base) ECREG(base + 0x03) -#define IT8XXX2_I2C_DHTR(base) ECREG(base + 0x04) -#define IT8XXX2_I2C_TOR(base) ECREG(base + 0x05) -#define IT8XXX2_I2C_DTR(base) ECREG(base + 0x08) -#define IT8XXX2_I2C_CTR(base) ECREG(base + 0x09) -#define IT8XXX2_I2C_CTR1(base) ECREG(base + 0x0A) -#define IT8XXX2_I2C_BYTE_CNT_H(base) ECREG(base + 0x0B) -#define IT8XXX2_I2C_BYTE_CNT_L(base) ECREG(base + 0x0C) -#define IT8XXX2_I2C_IRQ_ST(base) ECREG(base + 0x0D) -#define IT8XXX2_I2C_IDR(base) ECREG(base + 0x06) -#define IT8XXX2_I2C_TOS(base) ECREG(base + 0x07) -#define IT8XXX2_I2C_SLV_NUM_H(base) ECREG(base + 0x10) -#define IT8XXX2_I2C_SLV_NUM_L(base) ECREG(base + 0x11) -#define IT8XXX2_I2C_STR2(base) ECREG(base + 0x12) -#define IT8XXX2_I2C_NST(base) ECREG(base + 0x13) -#define IT8XXX2_I2C_TO_ARB_ST(base) ECREG(base + 0x18) -#define IT8XXX2_I2C_ERR_ST(base) ECREG(base + 0x19) -#define IT8XXX2_I2C_FST(base) ECREG(base + 0x1B) -#define IT8XXX2_I2C_EM(base) ECREG(base + 0x1C) -#define IT8XXX2_I2C_MODE_SEL(base) ECREG(base + 0x1D) -#define IT8XXX2_I2C_IDR2(base) ECREG(base + 0x1F) -#define IT8XXX2_I2C_CTR2(base) ECREG(base + 0x20) -#define IT8XXX2_I2C_RAMHA(base) ECREG(base + 0x23) -#define IT8XXX2_I2C_RAMLA(base) ECREG(base + 0x24) -#define IT8XXX2_I2C_RAMHA2(base) ECREG(base + 0x2C) -#define IT8XXX2_I2C_RAMLA2(base) ECREG(base + 0x2D) -#define IT8XXX2_I2C_CMD_ADDH(base) ECREG(base + 0x25) -#define IT8XXX2_I2C_CMD_ADDL(base) ECREG(base + 0x26) -#define IT8XXX2_I2C_RAMH2A(base) ECREG(base + 0x50) -#define IT8XXX2_I2C_CMD_ADDH2(base) ECREG(base + 0x52) +#define IT8XXX2_I2C_DRR(base) ECREG(base + 0x00) +#define IT8XXX2_I2C_PSR(base) ECREG(base + 0x01) +#define IT8XXX2_I2C_HSPR(base) ECREG(base + 0x02) +#define IT8XXX2_I2C_STR(base) ECREG(base + 0x03) +#define IT8XXX2_I2C_DHTR(base) ECREG(base + 0x04) +#define IT8XXX2_I2C_TOR(base) ECREG(base + 0x05) +#define IT8XXX2_I2C_DTR(base) ECREG(base + 0x08) +#define IT8XXX2_I2C_CTR(base) ECREG(base + 0x09) +#define IT8XXX2_I2C_CTR1(base) ECREG(base + 0x0A) +#define IT8XXX2_I2C_BYTE_CNT_H(base) ECREG(base + 0x0B) +#define IT8XXX2_I2C_BYTE_CNT_L(base) ECREG(base + 0x0C) +#define IT8XXX2_I2C_IRQ_ST(base) ECREG(base + 0x0D) +#define IT8XXX2_I2C_IDR(base) ECREG(base + 0x06) +#define IT8XXX2_I2C_TOS(base) ECREG(base + 0x07) +#define IT8XXX2_I2C_SLV_NUM_H(base) ECREG(base + 0x10) +#define IT8XXX2_I2C_SLV_NUM_L(base) ECREG(base + 0x11) +#define IT8XXX2_I2C_STR2(base) ECREG(base + 0x12) +#define IT8XXX2_I2C_NST(base) ECREG(base + 0x13) +#define IT8XXX2_I2C_TO_ARB_ST(base) ECREG(base + 0x18) +#define IT8XXX2_I2C_ERR_ST(base) ECREG(base + 0x19) +#define IT8XXX2_I2C_FST(base) ECREG(base + 0x1B) +#define IT8XXX2_I2C_EM(base) ECREG(base + 0x1C) +#define IT8XXX2_I2C_MODE_SEL(base) ECREG(base + 0x1D) +#define IT8XXX2_I2C_IDR2(base) ECREG(base + 0x1F) +#define IT8XXX2_I2C_CTR2(base) ECREG(base + 0x20) +#define IT8XXX2_I2C_RAMHA(base) ECREG(base + 0x23) +#define IT8XXX2_I2C_RAMLA(base) ECREG(base + 0x24) +#define IT8XXX2_I2C_RAMHA2(base) ECREG(base + 0x2C) +#define IT8XXX2_I2C_RAMLA2(base) ECREG(base + 0x2D) +#define IT8XXX2_I2C_CMD_ADDH(base) ECREG(base + 0x25) +#define IT8XXX2_I2C_CMD_ADDL(base) ECREG(base + 0x26) +#define IT8XXX2_I2C_RAMH2A(base) ECREG(base + 0x50) +#define IT8XXX2_I2C_CMD_ADDH2(base) ECREG(base + 0x52) /* SMBus/I2C register fields */ /* 0x09-0xB: SMCLK Timing Setting */ -#define IT8XXX2_SMB_SMCLKS_1M 4 -#define IT8XXX2_SMB_SMCLKS_400K 3 -#define IT8XXX2_SMB_SMCLKS_100K 2 -#define IT8XXX2_SMB_SMCLKS_50K 1 +#define IT8XXX2_SMB_SMCLKS_1M 4 +#define IT8XXX2_SMB_SMCLKS_400K 3 +#define IT8XXX2_SMB_SMCLKS_100K 2 +#define IT8XXX2_SMB_SMCLKS_50K 1 /* 0x0E: SMBus FIFO Status 1 */ -#define IT8XXX2_SMB_FIFO1_EMPTY BIT(7) -#define IT8XXX2_SMB_FIFO1_FULL BIT(6) +#define IT8XXX2_SMB_FIFO1_EMPTY BIT(7) +#define IT8XXX2_SMB_FIFO1_FULL BIT(6) /* 0x0D: SMBus FIFO Control 1 */ /* 0x0F: SMBus FIFO Control 2 */ -#define IT8XXX2_SMB_BLKDS BIT(4) -#define IT8XXX2_SMB_FFEN BIT(3) -#define IT8XXX2_SMB_FFCHSEL2_B 0 -#define IT8XXX2_SMB_FFCHSEL2_C BIT(0) +#define IT8XXX2_SMB_BLKDS BIT(4) +#define IT8XXX2_SMB_FFEN BIT(3) +#define IT8XXX2_SMB_FFCHSEL2_B 0 +#define IT8XXX2_SMB_FFCHSEL2_C BIT(0) /* 0x10: SMBus FIFO Status 2 */ -#define IT8XXX2_SMB_FIFO2_EMPTY BIT(7) -#define IT8XXX2_SMB_FIFO2_FULL BIT(6) +#define IT8XXX2_SMB_FIFO2_EMPTY BIT(7) +#define IT8XXX2_SMB_FIFO2_FULL BIT(6) /* 0x12: I2C Wr To Rd FIFO */ -#define IT8XXX2_SMB_MAIF BIT(7) -#define IT8XXX2_SMB_MBCIF BIT(6) -#define IT8XXX2_SMB_MCIFI BIT(2) -#define IT8XXX2_SMB_MBIFI BIT(1) -#define IT8XXX2_SMB_MAIFI BIT(0) +#define IT8XXX2_SMB_MAIF BIT(7) +#define IT8XXX2_SMB_MBCIF BIT(6) +#define IT8XXX2_SMB_MCIFI BIT(2) +#define IT8XXX2_SMB_MBIFI BIT(1) +#define IT8XXX2_SMB_MAIFI BIT(0) /* 0x13: I2C Wr To Rd FIFO Interrupt Status */ -#define IT8XXX2_SMB_MCIFID BIT(2) -#define IT8XXX2_SMB_MAIFID BIT(0) +#define IT8XXX2_SMB_MCIFID BIT(2) +#define IT8XXX2_SMB_MAIFID BIT(0) /* 0x41 0x81 0xC1: Host Control */ -#define IT8XXX2_SMB_SRT BIT(6) -#define IT8XXX2_SMB_LABY BIT(5) -#define IT8XXX2_SMB_SMCD_EXTND BIT(4) | BIT(3) | BIT(2) -#define IT8XXX2_SMB_KILL BIT(1) -#define IT8XXX2_SMB_INTREN BIT(0) +#define IT8XXX2_SMB_SRT BIT(6) +#define IT8XXX2_SMB_LABY BIT(5) +#define IT8XXX2_SMB_SMCD_EXTND BIT(4) | BIT(3) | BIT(2) +#define IT8XXX2_SMB_KILL BIT(1) +#define IT8XXX2_SMB_INTREN BIT(0) /* 0x43 0x83 0xC3: Transmit Slave Address */ -#define IT8XXX2_SMB_DIR BIT(0) +#define IT8XXX2_SMB_DIR BIT(0) /* 0x4A 0x8A 0xCA: SMBus Pin Control */ -#define IT8XXX2_SMB_SMBDCS BIT(1) -#define IT8XXX2_SMB_SMBCS BIT(0) +#define IT8XXX2_SMB_SMBDCS BIT(1) +#define IT8XXX2_SMB_SMBCS BIT(0) /* 0x50 0x90 0xD0: Host Control 2 */ -#define IT8XXX2_SMB_SMD_TO_EN BIT(4) -#define IT8XXX2_SMB_I2C_SW_EN BIT(3) -#define IT8XXX2_SMB_I2C_SW_WAIT BIT(2) -#define IT8XXX2_SMB_I2C_EN BIT(1) -#define IT8XXX2_SMB_SMHEN BIT(0) +#define IT8XXX2_SMB_SMD_TO_EN BIT(4) +#define IT8XXX2_SMB_I2C_SW_EN BIT(3) +#define IT8XXX2_SMB_I2C_SW_WAIT BIT(2) +#define IT8XXX2_SMB_I2C_EN BIT(1) +#define IT8XXX2_SMB_SMHEN BIT(0) /* 0x55: Slave A FIFO Control */ -#define IT8XXX2_SMB_HSAPE BIT(1) +#define IT8XXX2_SMB_HSAPE BIT(1) /* 0x03: Status Register */ -#define IT8XXX2_I2C_BYTE_DONE BIT(7) -#define IT8XXX2_I2C_RW BIT(2) -#define IT8XXX2_I2C_INT_PEND BIT(1) +#define IT8XXX2_I2C_BYTE_DONE BIT(7) +#define IT8XXX2_I2C_RW BIT(2) +#define IT8XXX2_I2C_INT_PEND BIT(1) /* 0x04: Data Hold Time */ -#define IT8XXX2_I2C_SOFT_RST BIT(7) +#define IT8XXX2_I2C_SOFT_RST BIT(7) /* 0x07: Time Out Status */ -#define IT8XXX2_I2C_CLK_STRETCH BIT(7) -#define IT8XXX2_I2C_SCL_IN BIT(2) -#define IT8XXX2_I2C_SDA_IN BIT(0) +#define IT8XXX2_I2C_CLK_STRETCH BIT(7) +#define IT8XXX2_I2C_SCL_IN BIT(2) +#define IT8XXX2_I2C_SDA_IN BIT(0) /* 0x09: Control Register */ -#define IT8XXX2_I2C_INT_EN BIT(6) -#define IT8XXX2_I2C_ACK BIT(3) -#define IT8XXX2_I2C_HALT BIT(0) +#define IT8XXX2_I2C_INT_EN BIT(6) +#define IT8XXX2_I2C_ACK BIT(3) +#define IT8XXX2_I2C_HALT BIT(0) /* 0x0A: Control 1 */ -#define IT8XXX2_I2C_COMQ_EN BIT(7) -#define IT8XXX2_I2C_MDL_EN BIT(1) +#define IT8XXX2_I2C_COMQ_EN BIT(7) +#define IT8XXX2_I2C_MDL_EN BIT(1) /* 0x0C: Byte count */ -#define IT8XXX2_I2C_DMA_ADDR_RELOAD BIT(5) -#define IT8XXX2_I2C_BYTE_CNT_ENABLE BIT(3) +#define IT8XXX2_I2C_DMA_ADDR_RELOAD BIT(5) +#define IT8XXX2_I2C_BYTE_CNT_ENABLE BIT(3) /* 0x0D: Interrupt Status */ -#define IT8XXX2_I2C_CNT_HOLD BIT(4) -#define IT8XXX2_I2C_IDW_CLR BIT(3) -#define IT8XXX2_I2C_IDR_CLR BIT(2) -#define IT8XXX2_I2C_SLVDATAFLG BIT(1) -#define IT8XXX2_I2C_P_CLR BIT(0) +#define IT8XXX2_I2C_CNT_HOLD BIT(4) +#define IT8XXX2_I2C_IDW_CLR BIT(3) +#define IT8XXX2_I2C_IDR_CLR BIT(2) +#define IT8XXX2_I2C_SLVDATAFLG BIT(1) +#define IT8XXX2_I2C_P_CLR BIT(0) /* 0x13: Nack Status */ -#define IT8XXX2_I2C_NST_CNS BIT(7) -#define IT8XXX2_I2C_NST_ID_NACK BIT(3) +#define IT8XXX2_I2C_NST_CNS BIT(7) +#define IT8XXX2_I2C_NST_ID_NACK BIT(3) /* 0x18: Timeout and Arbiter Status */ -#define IT8XXX2_I2C_SCL_TIMEOUT_EN BIT(7) -#define IT8XXX2_I2C_SDA_TIMEOUT_EN BIT(6) +#define IT8XXX2_I2C_SCL_TIMEOUT_EN BIT(7) +#define IT8XXX2_I2C_SDA_TIMEOUT_EN BIT(6) /* 0x19: Error Status */ -#define IT8XXX2_I2C_ERR_ST_DEV1_EIRQ BIT(0) +#define IT8XXX2_I2C_ERR_ST_DEV1_EIRQ BIT(0) /* 0x1B: Finish Status */ -#define IT8XXX2_I2C_FST_DEV1_IRQ BIT(4) +#define IT8XXX2_I2C_FST_DEV1_IRQ BIT(4) /* 0x1C: Error Mask */ -#define IT8XXX2_I2C_EM_DEV1_IRQ BIT(4) +#define IT8XXX2_I2C_EM_DEV1_IRQ BIT(4) /* * TODO: use gctrl_it8xxx2_regs instead of following register declarations @@ -1479,73 +1461,72 @@ enum chip_pll_mode { /* --- General Control (GCTRL) --- */ #define IT83XX_GCTRL_BASE 0x00F02000 -#define IT83XX_GCTRL_CHIPID1 ECREG(IT83XX_GCTRL_BASE + 0x85) -#define IT83XX_GCTRL_CHIPID2 ECREG(IT83XX_GCTRL_BASE + 0x86) -#define IT83XX_GCTRL_CHIPVER ECREG(IT83XX_GCTRL_BASE + 0x02) -#define IT83XX_GCTRL_MCCR3 ECREG(IT83XX_GCTRL_BASE + 0x20) -#define IT83XX_GCTRL_SPISLVPFE BIT(6) -#define IT83XX_GCTRL_EWPR0PFH(i) ECREG(IT83XX_GCTRL_BASE + 0x60 + i) -#define IT83XX_GCTRL_EWPR0PFD(i) ECREG(IT83XX_GCTRL_BASE + 0xA0 + i) -#define IT83XX_GCTRL_EWPR0PFEC(i) ECREG(IT83XX_GCTRL_BASE + 0xC0 + i) +#define IT83XX_GCTRL_CHIPID1 ECREG(IT83XX_GCTRL_BASE + 0x85) +#define IT83XX_GCTRL_CHIPID2 ECREG(IT83XX_GCTRL_BASE + 0x86) +#define IT83XX_GCTRL_CHIPVER ECREG(IT83XX_GCTRL_BASE + 0x02) +#define IT83XX_GCTRL_MCCR3 ECREG(IT83XX_GCTRL_BASE + 0x20) +#define IT83XX_GCTRL_SPISLVPFE BIT(6) +#define IT83XX_GCTRL_EWPR0PFH(i) ECREG(IT83XX_GCTRL_BASE + 0x60 + i) +#define IT83XX_GCTRL_EWPR0PFD(i) ECREG(IT83XX_GCTRL_BASE + 0xA0 + i) +#define IT83XX_GCTRL_EWPR0PFEC(i) ECREG(IT83XX_GCTRL_BASE + 0xC0 + i) /* * TODO: use spisc_it8xxx2_regs instead of following register declarations * to fix in cros_shi_it8xxx2.c. */ /* Serial Peripheral Interface (SPI) */ -#define IT83XX_SPI_BASE 0x00F03A00 +#define IT83XX_SPI_BASE 0x00F03A00 -#define IT83XX_SPI_SPISGCR ECREG(IT83XX_SPI_BASE + 0x00) -#define IT83XX_SPI_SPISCEN BIT(0) -#define IT83XX_SPI_TXRXFAR ECREG(IT83XX_SPI_BASE + 0x01) -#define IT83XX_SPI_CPURXF2A BIT(4) -#define IT83XX_SPI_CPURXF1A BIT(3) -#define IT83XX_SPI_CPUTFA BIT(1) -#define IT83XX_SPI_TXFCR ECREG(IT83XX_SPI_BASE + 0x02) -#define IT83XX_SPI_TXFCMR BIT(2) -#define IT83XX_SPI_TXFR BIT(1) -#define IT83XX_SPI_TXFS BIT(0) -#define IT83XX_SPI_GCR2 ECREG(IT83XX_SPI_BASE + 0x03) -#define IT83XX_SPI_RXF2OC BIT(4) -#define IT83XX_SPI_RXF1OC BIT(3) -#define IT83XX_SPI_RXFAR BIT(0) -#define IT83XX_SPI_IMR ECREG(IT83XX_SPI_BASE + 0x04) -#define IT83XX_SPI_RX_FIFO_FULL BIT(7) -#define IT83XX_SPI_RX_REACH BIT(5) -#define IT83XX_SPI_EDIM BIT(2) -#define IT83XX_SPI_ISR ECREG(IT83XX_SPI_BASE + 0x05) -#define IT83XX_SPI_TXFSR ECREG(IT83XX_SPI_BASE + 0x06) -#define IT83XX_SPI_ENDDETECTINT BIT(2) -#define IT83XX_SPI_RXFSR ECREG(IT83XX_SPI_BASE + 0x07) -#define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3)) -#define IT83XX_SPI_RXF2FS BIT(2) -#define IT83XX_SPI_RXF1FS BIT(1) -#define IT83XX_SPI_SPISRDR ECREG(IT83XX_SPI_BASE + 0x0b) -#define IT83XX_SPI_CPUWTFDB0 ECREG_u32(IT83XX_SPI_BASE + 0x08) -#define IT83XX_SPI_FCR ECREG(IT83XX_SPI_BASE + 0x09) -#define IT83XX_SPI_SPISRTXF BIT(2) -#define IT83XX_SPI_RXFR BIT(1) -#define IT83XX_SPI_RXFCMR BIT(0) -#define IT83XX_SPI_RXFRDRB0 ECREG_u32(IT83XX_SPI_BASE + 0x0C) -#define IT83XX_SPI_FTCB0R ECREG(IT83XX_SPI_BASE + 0x18) -#define IT83XX_SPI_FTCB1R ECREG(IT83XX_SPI_BASE + 0x19) -#define IT83XX_SPI_TCCB0 ECREG(IT83XX_SPI_BASE + 0x1A) -#define IT83XX_SPI_TCCB1 ECREG(IT83XX_SPI_BASE + 0x1B) -#define IT83XX_SPI_HPR2 ECREG(IT83XX_SPI_BASE + 0x1E) -#define IT83XX_SPI_EMMCBMR ECREG(IT83XX_SPI_BASE + 0x21) -#define IT83XX_SPI_EMMCABM BIT(1) /* eMMC Alternative Boot Mode */ -#define IT83XX_SPI_RX_VLISMR ECREG(IT83XX_SPI_BASE + 0x26) -#define IT83XX_SPI_RVLIM BIT(0) -#define IT83XX_SPI_RX_VLISR ECREG(IT83XX_SPI_BASE + 0x27) -#define IT83XX_SPI_RVLI BIT(0) +#define IT83XX_SPI_SPISGCR ECREG(IT83XX_SPI_BASE + 0x00) +#define IT83XX_SPI_SPISCEN BIT(0) +#define IT83XX_SPI_TXRXFAR ECREG(IT83XX_SPI_BASE + 0x01) +#define IT83XX_SPI_CPURXF2A BIT(4) +#define IT83XX_SPI_CPURXF1A BIT(3) +#define IT83XX_SPI_CPUTFA BIT(1) +#define IT83XX_SPI_TXFCR ECREG(IT83XX_SPI_BASE + 0x02) +#define IT83XX_SPI_TXFCMR BIT(2) +#define IT83XX_SPI_TXFR BIT(1) +#define IT83XX_SPI_TXFS BIT(0) +#define IT83XX_SPI_GCR2 ECREG(IT83XX_SPI_BASE + 0x03) +#define IT83XX_SPI_RXF2OC BIT(4) +#define IT83XX_SPI_RXF1OC BIT(3) +#define IT83XX_SPI_RXFAR BIT(0) +#define IT83XX_SPI_IMR ECREG(IT83XX_SPI_BASE + 0x04) +#define IT83XX_SPI_RX_FIFO_FULL BIT(7) +#define IT83XX_SPI_RX_REACH BIT(5) +#define IT83XX_SPI_EDIM BIT(2) +#define IT83XX_SPI_ISR ECREG(IT83XX_SPI_BASE + 0x05) +#define IT83XX_SPI_TXFSR ECREG(IT83XX_SPI_BASE + 0x06) +#define IT83XX_SPI_ENDDETECTINT BIT(2) +#define IT83XX_SPI_RXFSR ECREG(IT83XX_SPI_BASE + 0x07) +#define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3)) +#define IT83XX_SPI_RXF2FS BIT(2) +#define IT83XX_SPI_RXF1FS BIT(1) +#define IT83XX_SPI_SPISRDR ECREG(IT83XX_SPI_BASE + 0x0b) +#define IT83XX_SPI_CPUWTFDB0 ECREG_u32(IT83XX_SPI_BASE + 0x08) +#define IT83XX_SPI_FCR ECREG(IT83XX_SPI_BASE + 0x09) +#define IT83XX_SPI_SPISRTXF BIT(2) +#define IT83XX_SPI_RXFR BIT(1) +#define IT83XX_SPI_RXFCMR BIT(0) +#define IT83XX_SPI_RXFRDRB0 ECREG_u32(IT83XX_SPI_BASE + 0x0C) +#define IT83XX_SPI_FTCB0R ECREG(IT83XX_SPI_BASE + 0x18) +#define IT83XX_SPI_FTCB1R ECREG(IT83XX_SPI_BASE + 0x19) +#define IT83XX_SPI_TCCB0 ECREG(IT83XX_SPI_BASE + 0x1A) +#define IT83XX_SPI_TCCB1 ECREG(IT83XX_SPI_BASE + 0x1B) +#define IT83XX_SPI_HPR2 ECREG(IT83XX_SPI_BASE + 0x1E) +#define IT83XX_SPI_EMMCBMR ECREG(IT83XX_SPI_BASE + 0x21) +#define IT83XX_SPI_EMMCABM BIT(1) /* eMMC Alternative Boot Mode */ +#define IT83XX_SPI_RX_VLISMR ECREG(IT83XX_SPI_BASE + 0x26) +#define IT83XX_SPI_RVLIM BIT(0) +#define IT83XX_SPI_RX_VLISR ECREG(IT83XX_SPI_BASE + 0x27) +#define IT83XX_SPI_RVLI BIT(0) /** * * (20xxh) General Control (GCTRL) registers * */ -#define GCTRL_IT8XXX2_REGS_BASE \ - ((struct gctrl_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gctrl))) +#define GCTRL_IT8XXX2_REGS_BASE ((struct gctrl_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gctrl))) #ifndef __ASSEMBLER__ struct gctrl_it8xxx2_regs { @@ -1644,45 +1625,45 @@ struct gctrl_it8xxx2_regs { /* GCTRL register fields */ /* 0x03: DBGR Operate Status */ -#define IT8XXX2_GCTRL_SMB_DBGR BIT(0) +#define IT8XXX2_GCTRL_SMB_DBGR BIT(0) /* 0x06: Reset Status */ -#define IT8XXX2_GCTRL_LRS (BIT(1) | BIT(0)) -#define IT8XXX2_GCTRL_IWDTR BIT(1) +#define IT8XXX2_GCTRL_LRS (BIT(1) | BIT(0)) +#define IT8XXX2_GCTRL_IWDTR BIT(1) /* 0x0B: Wait Next 65K Rising */ -#define IT8XXX2_GCTRL_WN65K 0x00 +#define IT8XXX2_GCTRL_WN65K 0x00 /* 0x10: Reset Control DMM */ -#define IT8XXX2_GCTRL_UART1SD BIT(3) -#define IT8XXX2_GCTRL_UART2SD BIT(2) +#define IT8XXX2_GCTRL_UART1SD BIT(3) +#define IT8XXX2_GCTRL_UART2SD BIT(2) /* 0x11: Reset Control 4 */ -#define IT8XXX2_GCTRL_RPECI BIT(4) -#define IT8XXX2_GCTRL_RUART2 BIT(2) -#define IT8XXX2_GCTRL_RUART1 BIT(1) +#define IT8XXX2_GCTRL_RPECI BIT(4) +#define IT8XXX2_GCTRL_RUART2 BIT(2) +#define IT8XXX2_GCTRL_RUART1 BIT(1) /* 0x1C: Special Control 4 */ -#define IT8XXX2_GCTRL_LRSIWR BIT(2) -#define IT8XXX2_GCTRL_LRSIPWRSWTR BIT(1) -#define IT8XXX2_GCTRL_LRSIPGWR BIT(0) +#define IT8XXX2_GCTRL_LRSIWR BIT(2) +#define IT8XXX2_GCTRL_LRSIPWRSWTR BIT(1) +#define IT8XXX2_GCTRL_LRSIPGWR BIT(0) /* 0x20: Memory Controller Configuration 3 */ -#define IT8XXX2_GCTRL_SPISLVPFE BIT(6) +#define IT8XXX2_GCTRL_SPISLVPFE BIT(6) /* 0x30: Memory Controller Configuration */ -#define IT8XXX2_GCTRL_USB_DEBUG_EN BIT(7) -#define IT8XXX2_GCTRL_ICACHE_RESET BIT(4) +#define IT8XXX2_GCTRL_USB_DEBUG_EN BIT(7) +#define IT8XXX2_GCTRL_ICACHE_RESET BIT(4) /* 0x37: Eflash Protect Lock */ -#define IT8XXX2_GCTRL_EPLR_ENABLE BIT(0) +#define IT8XXX2_GCTRL_EPLR_ENABLE BIT(0) /* 0x46: Pin Multi-function Enable 3 */ -#define IT8XXX2_GCTRL_SMB3PSEL BIT(6) -#define IT8XXX2_GCTRL_SRAM_CRYPTO_USED BIT(5) +#define IT8XXX2_GCTRL_SMB3PSEL BIT(6) +#define IT8XXX2_GCTRL_SRAM_CRYPTO_USED BIT(5) /* 0x4B: ETWD and UART Control */ -#define IT8XXX2_GCTRL_ETWD_HW_RST_EN BIT(0) +#define IT8XXX2_GCTRL_ETWD_HW_RST_EN BIT(0) /* 0x5D: RISCV ILM Configuration 0 */ -#define IT8XXX2_GCTRL_ILM0_ENABLE BIT(0) +#define IT8XXX2_GCTRL_ILM0_ENABLE BIT(0) /* Accept Port 80h Cycle */ -#define IT8XXX2_GCTRL_ACP80 BIT(6) +#define IT8XXX2_GCTRL_ACP80 BIT(6) /* Accept Port 81h Cycle */ -#define IT8XXX2_GCTRL_ACP81 BIT(3) +#define IT8XXX2_GCTRL_ACP81 BIT(3) /* USB Debug Enable */ -#define IT8XXX2_GCTRL_MCCR_USB_EN BIT(7) +#define IT8XXX2_GCTRL_MCCR_USB_EN BIT(7) /* USB Pad Power-On Enable */ -#define IT8XXX2_GCTRL_PMER2_USB_PAD_EN BIT(7) +#define IT8XXX2_GCTRL_PMER2_USB_PAD_EN BIT(7) /* * VCC Detector Option. @@ -1691,15 +1672,15 @@ struct gctrl_it8xxx2_regs { * PECI). It means VCC should be logic high before using these * functions, or firmware treats VCC logic high. */ -#define IT8XXX2_GCTRL_VCCDO_MASK (BIT(6) | BIT(7)) -#define IT8XXX2_GCTRL_VCCDO_VCC_ON BIT(6) +#define IT8XXX2_GCTRL_VCCDO_MASK (BIT(6) | BIT(7)) +#define IT8XXX2_GCTRL_VCCDO_VCC_ON BIT(6) /* * bit[3] = 0: The reset source of PNPCFG is RSTPNP bit in RSTCH * register and WRST#. */ -#define IT8XXX2_GCTRL_HGRST BIT(3) +#define IT8XXX2_GCTRL_HGRST BIT(3) /* bit[2] = 1: Enable global reset. */ -#define IT8XXX2_GCTRL_GRST BIT(2) +#define IT8XXX2_GCTRL_GRST BIT(2) /** * @@ -1886,8 +1867,7 @@ struct kbc_regs { #define KBC_KBHISR_IBF BIT(1) /* A2 Address (A2) */ #define KBC_KBHISR_A2_ADDR BIT(3) -#define KBC_KBHISR_STS_MASK (KBC_KBHISR_OBF | KBC_KBHISR_IBF \ - | KBC_KBHISR_A2_ADDR) +#define KBC_KBHISR_STS_MASK (KBC_KBHISR_OBF | KBC_KBHISR_IBF | KBC_KBHISR_A2_ADDR) /* Clear Output Buffer Full */ #define KBC_KBHICR_COBF BIT(6) @@ -1953,20 +1933,20 @@ struct pmc_regs { }; /* Input Buffer Full Interrupt Enable */ -#define PMC_PM1CTL_IBFIE BIT(0) +#define PMC_PM1CTL_IBFIE BIT(0) /* Output Buffer Full */ -#define PMC_PM1STS_OBF BIT(0) +#define PMC_PM1STS_OBF BIT(0) /* Input Buffer Full */ -#define PMC_PM1STS_IBF BIT(1) +#define PMC_PM1STS_IBF BIT(1) /* General Purpose Flag */ -#define PMC_PM1STS_GPF BIT(2) +#define PMC_PM1STS_GPF BIT(2) /* A2 Address (A2) */ -#define PMC_PM1STS_A2_ADDR BIT(3) +#define PMC_PM1STS_A2_ADDR BIT(3) /* PMC2 Input Buffer Full Interrupt Enable */ -#define PMC_PM2CTL_IBFIE BIT(0) +#define PMC_PM2CTL_IBFIE BIT(0) /* General Purpose Flag */ -#define PMC_PM2STS_GPF BIT(2) +#define PMC_PM2STS_GPF BIT(2) /* * Dedicated Interrupt @@ -1979,7 +1959,7 @@ struct pmc_regs { * INT26: PMC2 Output Buffer Empty Int * INT27: PMC2 Input Buffer Full Int */ -#define PMC_MBXCTRL_DINT BIT(5) +#define PMC_MBXCTRL_DINT BIT(5) /* * eSPI slave registers @@ -2184,7 +2164,6 @@ struct espi_queue1_regs { #endif /* !__ASSEMBLER__ */ - /** * * (3Axxh) SPI Slave Controller (SPISC) registers @@ -2249,29 +2228,29 @@ struct spisc_it8xxx2_regs { /* SPISC register fields */ /* 0x00: SPI Slave General Control */ -#define IT8XXX2_SPISC_SPISCEN BIT(0) +#define IT8XXX2_SPISC_SPISCEN BIT(0) /* 0x01: Tx/Rx FIFO Access */ -#define IT8XXX2_SPISC_CPURXF1A BIT(3) -#define IT8XXX2_SPISC_CPUTFA BIT(1) +#define IT8XXX2_SPISC_CPURXF1A BIT(3) +#define IT8XXX2_SPISC_CPUTFA BIT(1) /* 0x02: Tx FIFO Control */ -#define IT8XXX2_SPISC_TXFCMR BIT(2) -#define IT8XXX2_SPISC_TXFR BIT(1) -#define IT8XXX2_SPISC_TXFS BIT(0) +#define IT8XXX2_SPISC_TXFCMR BIT(2) +#define IT8XXX2_SPISC_TXFR BIT(1) +#define IT8XXX2_SPISC_TXFS BIT(0) /* 0x03: SPI Slave General Control 2 */ -#define IT8XXX2_SPISC_RXF2OC BIT(4) -#define IT8XXX2_SPISC_RXF1OC BIT(3) -#define IT8XXX2_SPISC_RXFAR BIT(0) +#define IT8XXX2_SPISC_RXF2OC BIT(4) +#define IT8XXX2_SPISC_RXF1OC BIT(3) +#define IT8XXX2_SPISC_RXFAR BIT(0) /* 0x04: Interrupt Mask */ -#define IT8XXX2_SPISC_EDIM BIT(2) +#define IT8XXX2_SPISC_EDIM BIT(2) /* 0x06: Tx FIFO Status */ -#define IT8XXX2_SPISC_ENDDETECTINT BIT(2) +#define IT8XXX2_SPISC_ENDDETECTINT BIT(2) /* 0x09: FIFO Control */ -#define IT8XXX2_SPISC_SPISRTXF BIT(2) -#define IT8XXX2_SPISC_RXFR BIT(1) -#define IT8XXX2_SPISC_RXFCMR BIT(0) +#define IT8XXX2_SPISC_SPISRTXF BIT(2) +#define IT8XXX2_SPISC_RXFR BIT(1) +#define IT8XXX2_SPISC_RXFCMR BIT(0) /* 0x26: Rx Valid Length Interrupt Status Mask */ -#define IT8XXX2_SPISC_RVLIM BIT(0) +#define IT8XXX2_SPISC_RVLIM BIT(0) /* 0x27: Rx Valid Length Interrupt Status */ -#define IT8XXX2_SPISC_RVLI BIT(0) +#define IT8XXX2_SPISC_RVLI BIT(0) #endif /* CHIP_CHIPREGS_H */