soc/intel_adsp: Unify HP-SRAM definition
The HP SRAM block address and size is specified in four different ways (devicetree, "SRAM_*", "HP_SRAM_*" and "L2_SRAM_*" macros). Unify, moving the C definition (which just fetches it from dts) to a single header and out of the platform layer. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross
Anas Nashif
parent
411d8b9624
commit
c6e0ada4bf
9 changed files with 47 additions and 61 deletions
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@ -7,6 +7,7 @@
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#define __INC_MEMORY_H
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#include <cavs-vectors.h>
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#include <cavs-mem.h>
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/* L2 HP SRAM */
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#define HP_RAM_RESERVE_HEADER_SPACE (HP_SRAM_WIN0_SIZE + \
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@ -16,20 +17,14 @@
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SRAM_DEBUG_SIZE + \
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SRAM_TRACE_SIZE)
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#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#define SRAM_BASE (L2_SRAM_BASE)
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#define SRAM_SIZE (L2_SRAM_SIZE)
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/* text and data share the same L2 HP SRAM.
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* So, they lie next to each other.
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*/
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#define RAM_BASE \
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(SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
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(L2_SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
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#define RAM_SIZE \
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(SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
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(L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
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#define LPSRAM_MASK(x) 0x00000003
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@ -44,10 +39,6 @@
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/* bootloader */
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#define HP_SRAM_BASE 0xbe000000
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#define HP_SRAM_SIZE (512 * 1024)
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#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
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/* boot loader in IMR */
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB000A000
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#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120
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@ -66,7 +57,7 @@
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#define IMR_BOOT_LDR_BSS_BASE 0xb0100000
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#define IMR_BOOT_LDR_BSS_SIZE 0x10000
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#define BOOT_LDR_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - \
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#define BOOT_LDR_STACK_BASE (L2_SRAM_BASE + L2_SRAM_SIZE - \
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BOOT_LDR_STACK_SIZE)
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#define BOOT_LDR_STACK_SIZE (4 * 0x1000)
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@ -7,24 +7,19 @@
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#define __INC_MEMORY_H
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#include <cavs/cpu.h>
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#include <cavs-mem.h>
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/* L2 HP SRAM */
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#define HP_RAM_RESERVE_HEADER_SPACE 0x00010000
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#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#define SRAM_BASE (L2_SRAM_BASE)
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#define SRAM_SIZE (L2_SRAM_SIZE)
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/* text and data share the same L2 HP SRAM.
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* So, they lie next to each other.
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*/
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#define RAM_BASE \
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(SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
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(L2_SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
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#define RAM_SIZE \
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(SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
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(L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
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#define LPSRAM_MASK(x) 0x00000003
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@ -39,10 +34,6 @@
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/* bootloader */
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#define HP_SRAM_BASE 0xbe000000
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#define HP_SRAM_SIZE (3008 * 1024)
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#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
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/* boot loader in IMR */
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000
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#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120
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@ -61,7 +52,7 @@
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#define IMR_BOOT_LDR_BSS_BASE 0xb0100000
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#define IMR_BOOT_LDR_BSS_SIZE 0x1000
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#define BOOT_LDR_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - \
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#define BOOT_LDR_STACK_BASE (L2_SRAM_BASE + L2_SRAM_SIZE - \
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BOOT_LDR_STACK_SIZE)
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#define BOOT_LDR_STACK_SIZE (4 * 0x1000)
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@ -104,7 +95,7 @@
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/* HP SRAM windows */
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/* window 0 */
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#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000)
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#define SRAM_SW_REG_BASE (L2_SRAM_BASE + 0x4000)
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#define SRAM_SW_REG_SIZE 0x1000
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#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
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@ -7,24 +7,19 @@
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#define __INC_MEMORY_H
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#include <cavs/cpu.h>
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#include <cavs-mem.h>
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/* L2 HP SRAM */
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#define HP_RAM_RESERVE_HEADER_SPACE 0x00010000
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#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#define SRAM_BASE (L2_SRAM_BASE)
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#define SRAM_SIZE (L2_SRAM_SIZE)
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/* text and data share the same L2 HP SRAM.
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* So, they lie next to each other.
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*/
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#define RAM_BASE \
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(SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
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(L2_SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
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#define RAM_SIZE \
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(SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
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(L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
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#define LPSRAM_MASK(x) 0x00000003
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@ -39,10 +34,6 @@
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/* bootloader */
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#define HP_SRAM_BASE 0xbe000000
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#define HP_SRAM_SIZE (3008 * 1024)
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#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
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/* boot loader in IMR */
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000
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#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120
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@ -61,7 +52,7 @@
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#define IMR_BOOT_LDR_BSS_BASE 0xb0100000
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#define IMR_BOOT_LDR_BSS_SIZE 0x1000
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#define BOOT_LDR_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - \
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#define BOOT_LDR_STACK_BASE (L2_SRAM_BASE + L2_SRAM_SIZE - \
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BOOT_LDR_STACK_SIZE)
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#define BOOT_LDR_STACK_SIZE (4 * 0x1000)
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@ -105,7 +96,7 @@
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/* HP SRAM windows */
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/* window 0 */
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#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000)
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#define SRAM_SW_REG_BASE (L2_SRAM_BASE + 0x4000)
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#define SRAM_SW_REG_SIZE 0x1000
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#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
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@ -7,24 +7,19 @@
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#define __INC_MEMORY_H
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#include <cavs/cpu.h>
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#include <cavs-mem.h>
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/* L2 HP SRAM */
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#define HP_RAM_RESERVE_HEADER_SPACE 0x00010000
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#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#define SRAM_BASE (L2_SRAM_BASE)
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#define SRAM_SIZE (L2_SRAM_SIZE)
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/* text and data share the same L2 HP SRAM.
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* So, they lie next to each other.
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*/
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#define RAM_BASE \
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(SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
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(L2_SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
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#define RAM_SIZE \
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(SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
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(L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
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#define LPSRAM_MASK(x) 0x00000003
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@ -39,12 +34,6 @@
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#define SRAM_BANK_SIZE (64 * 1024)
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/* bootloader */
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#define HP_SRAM_BASE 0xbe000000
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#define HP_SRAM_SIZE (30 * SRAM_BANK_SIZE)
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#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
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/* boot loader in IMR */
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000
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#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120
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@ -63,7 +52,7 @@
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#define IMR_BOOT_LDR_BSS_BASE 0xb0100000
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#define IMR_BOOT_LDR_BSS_SIZE 0x1000
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#define BOOT_LDR_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - \
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#define BOOT_LDR_STACK_BASE (L2_SRAM_BASE + L2_SRAM_SIZE - \
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BOOT_LDR_STACK_SIZE)
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#define BOOT_LDR_STACK_SIZE (4 * 0x1000)
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@ -106,7 +95,7 @@
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/* HP SRAM windows */
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/* window 0 */
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#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000)
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#define SRAM_SW_REG_BASE (L2_SRAM_BASE + 0x4000)
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#define SRAM_SW_REG_SIZE 0x1000
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#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
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@ -4,13 +4,21 @@
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#
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add_library(base_module OBJECT base_module.c)
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target_include_directories(base_module PUBLIC
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${SOC_DIR}/${ARCH}/${SOC_PATH}/
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${SOC_DIR}/${ARCH}/${SOC_PATH}/include
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${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include
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${PROJECT_BINARY_DIR}/include/generated
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${ZEPHYR_BASE}/include
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../include
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)
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add_library(boot_module OBJECT boot_module.c)
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target_include_directories(boot_module PUBLIC
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${SOC_DIR}/${ARCH}/${SOC_PATH}/
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${SOC_DIR}/${ARCH}/${SOC_PATH}/include
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${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include
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${PROJECT_BINARY_DIR}/include/generated
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${ZEPHYR_BASE}/include
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../include
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)
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@ -49,8 +57,11 @@ add_custom_command(TARGET bootloader
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-MD
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-D_LINKER
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-D_ASMLANGUAGE
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-I ${SOC_DIR}/${ARCH}/${SOC_PATH}/
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-I ${SOC_DIR}/${ARCH}/${SOC_PATH}/include
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-I ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include
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-I ${PROJECT_BINARY_DIR}/include/generated
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-I ${ZEPHYR_BASE}/include
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${current_defines}
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${linker_pass_define}
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-E ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/bootloader/${bootloader_linker_script}.x
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@ -52,7 +52,7 @@ l2_cache_pref:
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#endif
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sof_stack_base:
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.word SOF_STACK_BASE
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.word L2_SRAM_BASE + L2_SRAM_SIZE
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wnd0_base:
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.word DMWBA(0)
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@ -150,7 +150,7 @@ static uint32_t get_fw_size_in_use(void)
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if (mod->segment[i].flags.r.type
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== SOF_MAN_SEGMENT_BSS) {
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fw_size_in_use = mod->segment[i].v_base_addr
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- HP_SRAM_BASE
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- L2_SRAM_BASE
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+ (mod->segment[i].flags.r.length
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* HOST_PAGE_SIZE);
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}
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@ -274,7 +274,7 @@ static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size)
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static int32_t hp_sram_init(void)
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{
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return hp_sram_power_on_memory(HP_SRAM_SIZE);
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return hp_sram_power_on_memory(L2_SRAM_SIZE);
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}
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#else
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13
soc/xtensa/intel_adsp/common/include/cavs-mem.h
Normal file
13
soc/xtensa/intel_adsp/common/include/cavs-mem.h
Normal file
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@ -0,0 +1,13 @@
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/* Copyright (c) 2021 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ZEPHYR_SOC_INTEL_ADSP_MEM
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#define _ZEPHYR_SOC_INTEL_ADSP_MEM
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#include <devicetree.h>
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#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#endif /* _ZEPHYR_SOC_INTEL_ADSP_MEM */
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@ -18,7 +18,7 @@
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/* This is the base address of all the vectors defined in SRAM */
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#define XCHAL_VECBASE_RESET_PADDR_SRAM \
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(SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE)
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(L2_SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE)
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#define MEM_VECBASE_LIT_SIZE 0x178
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