diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
index a31077f3d1c..bcff4490a8b 100644
--- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
@@ -7,6 +7,7 @@
 #define __INC_MEMORY_H
 
 #include <cavs-vectors.h>
+#include <cavs-mem.h>
 
 /* L2 HP SRAM */
 #define HP_RAM_RESERVE_HEADER_SPACE	(HP_SRAM_WIN0_SIZE + \
@@ -16,20 +17,14 @@
 					 SRAM_DEBUG_SIZE + \
 					 SRAM_TRACE_SIZE)
 
-#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
-#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
-
-#define SRAM_BASE (L2_SRAM_BASE)
-#define SRAM_SIZE (L2_SRAM_SIZE)
-
 /* text and data share the same L2 HP SRAM.
  * So, they lie next to each other.
  */
 #define RAM_BASE \
-	(SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
+	(L2_SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
 
 #define RAM_SIZE \
-	(SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
+	(L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
 
 #define LPSRAM_MASK(x)		0x00000003
 
@@ -44,10 +39,6 @@
 
 /* bootloader */
 
-#define HP_SRAM_BASE	0xbe000000
-#define HP_SRAM_SIZE	(512 * 1024)
-#define SOF_STACK_BASE	(HP_SRAM_BASE + HP_SRAM_SIZE)
-
 /* boot loader in IMR */
 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE	0xB000A000
 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE	0x120
@@ -66,7 +57,7 @@
 #define IMR_BOOT_LDR_BSS_BASE	0xb0100000
 #define IMR_BOOT_LDR_BSS_SIZE	0x10000
 
-#define BOOT_LDR_STACK_BASE		(HP_SRAM_BASE + HP_SRAM_SIZE - \
+#define BOOT_LDR_STACK_BASE		(L2_SRAM_BASE + L2_SRAM_SIZE - \
 					BOOT_LDR_STACK_SIZE)
 #define BOOT_LDR_STACK_SIZE		(4 * 0x1000)
 
diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
index e810e418567..cd4d45cd67d 100644
--- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
@@ -7,24 +7,19 @@
 #define __INC_MEMORY_H
 
 #include <cavs/cpu.h>
+#include <cavs-mem.h>
 
 /* L2 HP SRAM */
 #define HP_RAM_RESERVE_HEADER_SPACE		0x00010000
 
-#define L2_SRAM_BASE			(DT_REG_ADDR(DT_NODELABEL(sram0)))
-#define L2_SRAM_SIZE			(DT_REG_SIZE(DT_NODELABEL(sram0)))
-
-#define SRAM_BASE (L2_SRAM_BASE)
-#define SRAM_SIZE (L2_SRAM_SIZE)
-
 /* text and data share the same L2 HP SRAM.
  * So, they lie next to each other.
  */
 #define RAM_BASE \
-	(SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
+	(L2_SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
 
 #define RAM_SIZE \
-	(SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
+	(L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
 
 #define LPSRAM_MASK(x)		0x00000003
 
@@ -39,10 +34,6 @@
 
 /* bootloader */
 
-#define HP_SRAM_BASE	0xbe000000
-#define HP_SRAM_SIZE	(3008 * 1024)
-#define SOF_STACK_BASE	(HP_SRAM_BASE + HP_SRAM_SIZE)
-
 /* boot loader in IMR */
 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE	0xB0038000
 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE	0x120
@@ -61,7 +52,7 @@
 #define IMR_BOOT_LDR_BSS_BASE	0xb0100000
 #define IMR_BOOT_LDR_BSS_SIZE	0x1000
 
-#define BOOT_LDR_STACK_BASE		(HP_SRAM_BASE + HP_SRAM_SIZE - \
+#define BOOT_LDR_STACK_BASE		(L2_SRAM_BASE + L2_SRAM_SIZE - \
 					BOOT_LDR_STACK_SIZE)
 #define BOOT_LDR_STACK_SIZE		(4 * 0x1000)
 
@@ -104,7 +95,7 @@
 /* HP SRAM windows */
 
 /* window 0 */
-#define SRAM_SW_REG_BASE	(HP_SRAM_BASE + 0x4000)
+#define SRAM_SW_REG_BASE	(L2_SRAM_BASE + 0x4000)
 #define SRAM_SW_REG_SIZE	0x1000
 
 #define SRAM_OUTBOX_BASE	(SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
index 9424eaab62d..7074ee04f45 100644
--- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
@@ -7,24 +7,19 @@
 #define __INC_MEMORY_H
 
 #include <cavs/cpu.h>
+#include <cavs-mem.h>
 
 /* L2 HP SRAM */
 #define HP_RAM_RESERVE_HEADER_SPACE	0x00010000
 
-#define L2_SRAM_BASE			(DT_REG_ADDR(DT_NODELABEL(sram0)))
-#define L2_SRAM_SIZE			(DT_REG_SIZE(DT_NODELABEL(sram0)))
-
-#define SRAM_BASE (L2_SRAM_BASE)
-#define SRAM_SIZE (L2_SRAM_SIZE)
-
 /* text and data share the same L2 HP SRAM.
  * So, they lie next to each other.
  */
 #define RAM_BASE \
-	(SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
+	(L2_SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
 
 #define RAM_SIZE \
-	(SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
+	(L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
 
 #define LPSRAM_MASK(x)		0x00000003
 
@@ -39,10 +34,6 @@
 
 /* bootloader */
 
-#define HP_SRAM_BASE	0xbe000000
-#define HP_SRAM_SIZE	(3008 * 1024)
-#define SOF_STACK_BASE	(HP_SRAM_BASE + HP_SRAM_SIZE)
-
 /* boot loader in IMR */
 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE	0xB0038000
 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE	0x120
@@ -61,7 +52,7 @@
 #define IMR_BOOT_LDR_BSS_BASE	0xb0100000
 #define IMR_BOOT_LDR_BSS_SIZE	0x1000
 
-#define BOOT_LDR_STACK_BASE		(HP_SRAM_BASE + HP_SRAM_SIZE - \
+#define BOOT_LDR_STACK_BASE		(L2_SRAM_BASE + L2_SRAM_SIZE - \
 					BOOT_LDR_STACK_SIZE)
 #define BOOT_LDR_STACK_SIZE		(4 * 0x1000)
 
@@ -105,7 +96,7 @@
 
 /* HP SRAM windows */
 /* window 0 */
-#define SRAM_SW_REG_BASE	(HP_SRAM_BASE + 0x4000)
+#define SRAM_SW_REG_BASE	(L2_SRAM_BASE + 0x4000)
 #define SRAM_SW_REG_SIZE	0x1000
 
 #define SRAM_OUTBOX_BASE	(SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
index 4684137f30b..2225f268fb8 100644
--- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
@@ -7,24 +7,19 @@
 #define __INC_MEMORY_H
 
 #include <cavs/cpu.h>
+#include <cavs-mem.h>
 
 /* L2 HP SRAM */
 #define HP_RAM_RESERVE_HEADER_SPACE	0x00010000
 
-#define L2_SRAM_BASE			(DT_REG_ADDR(DT_NODELABEL(sram0)))
-#define L2_SRAM_SIZE			(DT_REG_SIZE(DT_NODELABEL(sram0)))
-
-#define SRAM_BASE (L2_SRAM_BASE)
-#define SRAM_SIZE (L2_SRAM_SIZE)
-
 /* text and data share the same L2 HP SRAM.
  * So, they lie next to each other.
  */
 #define RAM_BASE \
-	(SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
+	(L2_SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
 
 #define RAM_SIZE \
-	(SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
+	(L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
 
 #define LPSRAM_MASK(x)		0x00000003
 
@@ -39,12 +34,6 @@
 
 #define SRAM_BANK_SIZE	(64 * 1024)
 
-/* bootloader */
-
-#define HP_SRAM_BASE	0xbe000000
-#define HP_SRAM_SIZE	(30 * SRAM_BANK_SIZE)
-#define SOF_STACK_BASE	(HP_SRAM_BASE + HP_SRAM_SIZE)
-
 /* boot loader in IMR */
 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE	0xB0038000
 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE	0x120
@@ -63,7 +52,7 @@
 #define IMR_BOOT_LDR_BSS_BASE	0xb0100000
 #define IMR_BOOT_LDR_BSS_SIZE	0x1000
 
-#define BOOT_LDR_STACK_BASE		(HP_SRAM_BASE + HP_SRAM_SIZE - \
+#define BOOT_LDR_STACK_BASE		(L2_SRAM_BASE + L2_SRAM_SIZE - \
 					BOOT_LDR_STACK_SIZE)
 #define BOOT_LDR_STACK_SIZE		(4 * 0x1000)
 
@@ -106,7 +95,7 @@
 /* HP SRAM windows */
 
 /* window 0 */
-#define SRAM_SW_REG_BASE	(HP_SRAM_BASE + 0x4000)
+#define SRAM_SW_REG_BASE	(L2_SRAM_BASE + 0x4000)
 #define SRAM_SW_REG_SIZE	0x1000
 
 #define SRAM_OUTBOX_BASE	(SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
diff --git a/soc/xtensa/intel_adsp/common/bootloader/CMakeLists.txt b/soc/xtensa/intel_adsp/common/bootloader/CMakeLists.txt
index cd9960c0814..7b216c748a7 100644
--- a/soc/xtensa/intel_adsp/common/bootloader/CMakeLists.txt
+++ b/soc/xtensa/intel_adsp/common/bootloader/CMakeLists.txt
@@ -4,13 +4,21 @@
 #
 add_library(base_module OBJECT base_module.c)
 target_include_directories(base_module PUBLIC
+  ${SOC_DIR}/${ARCH}/${SOC_PATH}/
   ${SOC_DIR}/${ARCH}/${SOC_PATH}/include
+  ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include
+  ${PROJECT_BINARY_DIR}/include/generated
+  ${ZEPHYR_BASE}/include
   ../include
   )
 
 add_library(boot_module OBJECT boot_module.c)
 target_include_directories(boot_module PUBLIC
+  ${SOC_DIR}/${ARCH}/${SOC_PATH}/
   ${SOC_DIR}/${ARCH}/${SOC_PATH}/include
+  ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include
+  ${PROJECT_BINARY_DIR}/include/generated
+  ${ZEPHYR_BASE}/include
   ../include
   )
 
@@ -49,8 +57,11 @@ add_custom_command(TARGET bootloader
     -MD
     -D_LINKER
     -D_ASMLANGUAGE
+    -I ${SOC_DIR}/${ARCH}/${SOC_PATH}/
     -I ${SOC_DIR}/${ARCH}/${SOC_PATH}/include
     -I ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include
+    -I ${PROJECT_BINARY_DIR}/include/generated
+    -I ${ZEPHYR_BASE}/include
     ${current_defines}
     ${linker_pass_define}
     -E ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/bootloader/${bootloader_linker_script}.x
diff --git a/soc/xtensa/intel_adsp/common/bootloader/boot_entry.S b/soc/xtensa/intel_adsp/common/bootloader/boot_entry.S
index 349b979afe5..dc1233e179b 100644
--- a/soc/xtensa/intel_adsp/common/bootloader/boot_entry.S
+++ b/soc/xtensa/intel_adsp/common/bootloader/boot_entry.S
@@ -52,7 +52,7 @@ l2_cache_pref:
 #endif
 
 sof_stack_base:
-	.word SOF_STACK_BASE
+	.word L2_SRAM_BASE + L2_SRAM_SIZE
 
 wnd0_base:
 	.word DMWBA(0)
diff --git a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
index d361f5ca857..c32e7e9d137 100644
--- a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
+++ b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
@@ -150,7 +150,7 @@ static uint32_t get_fw_size_in_use(void)
 			if (mod->segment[i].flags.r.type
 				== SOF_MAN_SEGMENT_BSS) {
 				fw_size_in_use = mod->segment[i].v_base_addr
-				- HP_SRAM_BASE
+				- L2_SRAM_BASE
 				+ (mod->segment[i].flags.r.length
 				* HOST_PAGE_SIZE);
 			}
@@ -274,7 +274,7 @@ static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size)
 
 static int32_t hp_sram_init(void)
 {
-	return hp_sram_power_on_memory(HP_SRAM_SIZE);
+	return hp_sram_power_on_memory(L2_SRAM_SIZE);
 }
 
 #else
diff --git a/soc/xtensa/intel_adsp/common/include/cavs-mem.h b/soc/xtensa/intel_adsp/common/include/cavs-mem.h
new file mode 100644
index 00000000000..e2415db608e
--- /dev/null
+++ b/soc/xtensa/intel_adsp/common/include/cavs-mem.h
@@ -0,0 +1,13 @@
+/* Copyright (c) 2021 Intel Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _ZEPHYR_SOC_INTEL_ADSP_MEM
+#define _ZEPHYR_SOC_INTEL_ADSP_MEM
+
+#include <devicetree.h>
+
+#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
+#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
+
+#endif /* _ZEPHYR_SOC_INTEL_ADSP_MEM */
+
diff --git a/soc/xtensa/intel_adsp/common/include/cavs-vectors.h b/soc/xtensa/intel_adsp/common/include/cavs-vectors.h
index d1b7b7e3341..7c70d49f804 100644
--- a/soc/xtensa/intel_adsp/common/include/cavs-vectors.h
+++ b/soc/xtensa/intel_adsp/common/include/cavs-vectors.h
@@ -18,7 +18,7 @@
 
 /* This is the base address of all the vectors defined in SRAM */
 #define XCHAL_VECBASE_RESET_PADDR_SRAM \
-	(SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE)
+	(L2_SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE)
 
 #define MEM_VECBASE_LIT_SIZE                   0x178