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soc/intel_adsp: Unify HP-SRAM definition

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The HP SRAM block address and size is specified in four different ways
(devicetree, "SRAM_*", "HP_SRAM_*" and "L2_SRAM_*" macros).  Unify,
moving the C definition (which just fetches it from dts) to a single
header and out of the platform layer.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2021-10-19 10:50:25 -07:00 • committed by Anas Nashif
commit c6e0ada4bf
9 changed files with 47 additions and 61 deletions
Download patch file Download diff file Expand all files Collapse all files

17
soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
View file

@ -7,6 +7,7 @@
#define __INC_MEMORY_H #define __INC_MEMORY_H
#include <cavs-vectors.h> #include <cavs-vectors.h>
#include <cavs-mem.h>
/* L2 HP SRAM */ /* L2 HP SRAM */
#define HP_RAM_RESERVE_HEADER_SPACE (HP_SRAM_WIN0_SIZE + \ #define HP_RAM_RESERVE_HEADER_SPACE (HP_SRAM_WIN0_SIZE + \
@ -16,20 +17,14 @@
SRAM_DEBUG_SIZE + \ SRAM_DEBUG_SIZE + \
SRAM_TRACE_SIZE) SRAM_TRACE_SIZE)
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#define SRAM_BASE (L2_SRAM_BASE)
#define SRAM_SIZE (L2_SRAM_SIZE)
/* text and data share the same L2 HP SRAM. /* text and data share the same L2 HP SRAM.
* So, they lie next to each other. * So, they lie next to each other.
*/ */
#define RAM_BASE \ #define RAM_BASE \
(SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE) (L2_SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
#define RAM_SIZE \ #define RAM_SIZE \
(SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE) (L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
#define LPSRAM_MASK(x) 0x00000003 #define LPSRAM_MASK(x) 0x00000003
@ -44,10 +39,6 @@
/* bootloader */ /* bootloader */
#define HP_SRAM_BASE 0xbe000000
#define HP_SRAM_SIZE (512 * 1024)
#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
/* boot loader in IMR */ /* boot loader in IMR */
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB000A000 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB000A000
#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120
@ -66,7 +57,7 @@
#define IMR_BOOT_LDR_BSS_BASE 0xb0100000 #define IMR_BOOT_LDR_BSS_BASE 0xb0100000
#define IMR_BOOT_LDR_BSS_SIZE 0x10000 #define IMR_BOOT_LDR_BSS_SIZE 0x10000
#define BOOT_LDR_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - \ #define BOOT_LDR_STACK_BASE (L2_SRAM_BASE + L2_SRAM_SIZE - \
BOOT_LDR_STACK_SIZE) BOOT_LDR_STACK_SIZE)
#define BOOT_LDR_STACK_SIZE (4 * 0x1000) #define BOOT_LDR_STACK_SIZE (4 * 0x1000)

19
soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
View file

@ -7,24 +7,19 @@
#define __INC_MEMORY_H #define __INC_MEMORY_H
#include <cavs/cpu.h> #include <cavs/cpu.h>
#include <cavs-mem.h>
/* L2 HP SRAM */ /* L2 HP SRAM */
#define HP_RAM_RESERVE_HEADER_SPACE 0x00010000 #define HP_RAM_RESERVE_HEADER_SPACE 0x00010000
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#define SRAM_BASE (L2_SRAM_BASE)
#define SRAM_SIZE (L2_SRAM_SIZE)
/* text and data share the same L2 HP SRAM. /* text and data share the same L2 HP SRAM.
* So, they lie next to each other. * So, they lie next to each other.
*/ */
#define RAM_BASE \ #define RAM_BASE \
(SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE) (L2_SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
#define RAM_SIZE \ #define RAM_SIZE \
(SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE) (L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
#define LPSRAM_MASK(x) 0x00000003 #define LPSRAM_MASK(x) 0x00000003
@ -39,10 +34,6 @@
/* bootloader */ /* bootloader */
#define HP_SRAM_BASE 0xbe000000
#define HP_SRAM_SIZE (3008 * 1024)
#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
/* boot loader in IMR */ /* boot loader in IMR */
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000
#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120
@ -61,7 +52,7 @@
#define IMR_BOOT_LDR_BSS_BASE 0xb0100000 #define IMR_BOOT_LDR_BSS_BASE 0xb0100000
#define IMR_BOOT_LDR_BSS_SIZE 0x1000 #define IMR_BOOT_LDR_BSS_SIZE 0x1000
#define BOOT_LDR_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - \ #define BOOT_LDR_STACK_BASE (L2_SRAM_BASE + L2_SRAM_SIZE - \
BOOT_LDR_STACK_SIZE) BOOT_LDR_STACK_SIZE)
#define BOOT_LDR_STACK_SIZE (4 * 0x1000) #define BOOT_LDR_STACK_SIZE (4 * 0x1000)
@ -104,7 +95,7 @@
/* HP SRAM windows */ /* HP SRAM windows */
/* window 0 */ /* window 0 */
#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000) #define SRAM_SW_REG_BASE (L2_SRAM_BASE + 0x4000)
#define SRAM_SW_REG_SIZE 0x1000 #define SRAM_SW_REG_SIZE 0x1000
#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) #define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)

19
soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
View file

@ -7,24 +7,19 @@
#define __INC_MEMORY_H #define __INC_MEMORY_H
#include <cavs/cpu.h> #include <cavs/cpu.h>
#include <cavs-mem.h>
/* L2 HP SRAM */ /* L2 HP SRAM */
#define HP_RAM_RESERVE_HEADER_SPACE 0x00010000 #define HP_RAM_RESERVE_HEADER_SPACE 0x00010000
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#define SRAM_BASE (L2_SRAM_BASE)
#define SRAM_SIZE (L2_SRAM_SIZE)
/* text and data share the same L2 HP SRAM. /* text and data share the same L2 HP SRAM.
* So, they lie next to each other. * So, they lie next to each other.
*/ */
#define RAM_BASE \ #define RAM_BASE \
(SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE) (L2_SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
#define RAM_SIZE \ #define RAM_SIZE \
(SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE) (L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
#define LPSRAM_MASK(x) 0x00000003 #define LPSRAM_MASK(x) 0x00000003
@ -39,10 +34,6 @@
/* bootloader */ /* bootloader */
#define HP_SRAM_BASE 0xbe000000
#define HP_SRAM_SIZE (3008 * 1024)
#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
/* boot loader in IMR */ /* boot loader in IMR */
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000
#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120
@ -61,7 +52,7 @@
#define IMR_BOOT_LDR_BSS_BASE 0xb0100000 #define IMR_BOOT_LDR_BSS_BASE 0xb0100000
#define IMR_BOOT_LDR_BSS_SIZE 0x1000 #define IMR_BOOT_LDR_BSS_SIZE 0x1000
#define BOOT_LDR_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - \ #define BOOT_LDR_STACK_BASE (L2_SRAM_BASE + L2_SRAM_SIZE - \
BOOT_LDR_STACK_SIZE) BOOT_LDR_STACK_SIZE)
#define BOOT_LDR_STACK_SIZE (4 * 0x1000) #define BOOT_LDR_STACK_SIZE (4 * 0x1000)
@ -105,7 +96,7 @@
/* HP SRAM windows */ /* HP SRAM windows */
/* window 0 */ /* window 0 */
#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000) #define SRAM_SW_REG_BASE (L2_SRAM_BASE + 0x4000)
#define SRAM_SW_REG_SIZE 0x1000 #define SRAM_SW_REG_SIZE 0x1000
#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) #define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)

21
soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
View file

@ -7,24 +7,19 @@
#define __INC_MEMORY_H #define __INC_MEMORY_H
#include <cavs/cpu.h> #include <cavs/cpu.h>
#include <cavs-mem.h>
/* L2 HP SRAM */ /* L2 HP SRAM */
#define HP_RAM_RESERVE_HEADER_SPACE 0x00010000 #define HP_RAM_RESERVE_HEADER_SPACE 0x00010000
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#define SRAM_BASE (L2_SRAM_BASE)
#define SRAM_SIZE (L2_SRAM_SIZE)
/* text and data share the same L2 HP SRAM. /* text and data share the same L2 HP SRAM.
* So, they lie next to each other. * So, they lie next to each other.
*/ */
#define RAM_BASE \ #define RAM_BASE \
(SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE) (L2_SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
#define RAM_SIZE \ #define RAM_SIZE \
(SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE) (L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
#define LPSRAM_MASK(x) 0x00000003 #define LPSRAM_MASK(x) 0x00000003
@ -39,12 +34,6 @@
#define SRAM_BANK_SIZE (64 * 1024) #define SRAM_BANK_SIZE (64 * 1024)
/* bootloader */
#define HP_SRAM_BASE 0xbe000000
#define HP_SRAM_SIZE (30 * SRAM_BANK_SIZE)
#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
/* boot loader in IMR */ /* boot loader in IMR */
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000
#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120
@ -63,7 +52,7 @@
#define IMR_BOOT_LDR_BSS_BASE 0xb0100000 #define IMR_BOOT_LDR_BSS_BASE 0xb0100000
#define IMR_BOOT_LDR_BSS_SIZE 0x1000 #define IMR_BOOT_LDR_BSS_SIZE 0x1000
#define BOOT_LDR_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - \ #define BOOT_LDR_STACK_BASE (L2_SRAM_BASE + L2_SRAM_SIZE - \
BOOT_LDR_STACK_SIZE) BOOT_LDR_STACK_SIZE)
#define BOOT_LDR_STACK_SIZE (4 * 0x1000) #define BOOT_LDR_STACK_SIZE (4 * 0x1000)
@ -106,7 +95,7 @@
/* HP SRAM windows */ /* HP SRAM windows */
/* window 0 */ /* window 0 */
#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000) #define SRAM_SW_REG_BASE (L2_SRAM_BASE + 0x4000)
#define SRAM_SW_REG_SIZE 0x1000 #define SRAM_SW_REG_SIZE 0x1000
#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) #define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)

11
soc/xtensa/intel_adsp/common/bootloader/CMakeLists.txt
View file

@ -4,13 +4,21 @@
# #
add_library(base_module OBJECT base_module.c) add_library(base_module OBJECT base_module.c)
target_include_directories(base_module PUBLIC target_include_directories(base_module PUBLIC
${SOC_DIR}/${ARCH}/${SOC_PATH}/
${SOC_DIR}/${ARCH}/${SOC_PATH}/include ${SOC_DIR}/${ARCH}/${SOC_PATH}/include
${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include
${PROJECT_BINARY_DIR}/include/generated
${ZEPHYR_BASE}/include
../include ../include
) )
add_library(boot_module OBJECT boot_module.c) add_library(boot_module OBJECT boot_module.c)
target_include_directories(boot_module PUBLIC target_include_directories(boot_module PUBLIC
${SOC_DIR}/${ARCH}/${SOC_PATH}/
${SOC_DIR}/${ARCH}/${SOC_PATH}/include ${SOC_DIR}/${ARCH}/${SOC_PATH}/include
${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include
${PROJECT_BINARY_DIR}/include/generated
${ZEPHYR_BASE}/include
../include ../include
) )
@ -49,8 +57,11 @@ add_custom_command(TARGET bootloader
-MD -MD
-D_LINKER -D_LINKER
-D_ASMLANGUAGE -D_ASMLANGUAGE
-I ${SOC_DIR}/${ARCH}/${SOC_PATH}/
-I ${SOC_DIR}/${ARCH}/${SOC_PATH}/include -I ${SOC_DIR}/${ARCH}/${SOC_PATH}/include
-I ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include -I ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include
-I ${PROJECT_BINARY_DIR}/include/generated
-I ${ZEPHYR_BASE}/include
${current_defines} ${current_defines}
${linker_pass_define} ${linker_pass_define}
-E ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/bootloader/${bootloader_linker_script}.x -E ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/bootloader/${bootloader_linker_script}.x

2
soc/xtensa/intel_adsp/common/bootloader/boot_entry.S
View file

@ -52,7 +52,7 @@ l2_cache_pref:
#endif #endif
sof_stack_base: sof_stack_base:
.word SOF_STACK_BASE .word L2_SRAM_BASE + L2_SRAM_SIZE
wnd0_base: wnd0_base:
.word DMWBA(0) .word DMWBA(0)

4
soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
View file

@ -150,7 +150,7 @@ static uint32_t get_fw_size_in_use(void)
if (mod->segment[i].flags.r.type if (mod->segment[i].flags.r.type
== SOF_MAN_SEGMENT_BSS) { == SOF_MAN_SEGMENT_BSS) {
fw_size_in_use = mod->segment[i].v_base_addr fw_size_in_use = mod->segment[i].v_base_addr
- HP_SRAM_BASE - L2_SRAM_BASE
+ (mod->segment[i].flags.r.length + (mod->segment[i].flags.r.length
* HOST_PAGE_SIZE); * HOST_PAGE_SIZE);
} }
@ -274,7 +274,7 @@ static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size)
static int32_t hp_sram_init(void) static int32_t hp_sram_init(void)
{ {
return hp_sram_power_on_memory(HP_SRAM_SIZE); return hp_sram_power_on_memory(L2_SRAM_SIZE);
} }
#else #else

13
soc/xtensa/intel_adsp/common/include/cavs-mem.h Normal file
View file

@ -0,0 +1,13 @@
/* Copyright (c) 2021 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ZEPHYR_SOC_INTEL_ADSP_MEM
#define _ZEPHYR_SOC_INTEL_ADSP_MEM
#include <devicetree.h>
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#endif /* _ZEPHYR_SOC_INTEL_ADSP_MEM */

2
soc/xtensa/intel_adsp/common/include/cavs-vectors.h
View file

@ -18,7 +18,7 @@
/* This is the base address of all the vectors defined in SRAM */ /* This is the base address of all the vectors defined in SRAM */
#define XCHAL_VECBASE_RESET_PADDR_SRAM \ #define XCHAL_VECBASE_RESET_PADDR_SRAM \
(SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE) (L2_SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE)
#define MEM_VECBASE_LIT_SIZE 0x178 #define MEM_VECBASE_LIT_SIZE 0x178