drivers: display: add support for GD7965 display controller
Add support for GD7965 display controller. Signed-off-by: Johann Fischer <j.fischer@phytec.de>
This commit is contained in:
Johann Fischer
Anas Nashif
parent
e31b6a6ca2
commit
c68ac431cc
6 changed files with 619 additions and 0 deletions
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@ -9,6 +9,7 @@ zephyr_sources_ifdef(CONFIG_DUMMY_DISPLAY display_dummy.c)
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zephyr_sources_ifdef(CONFIG_FRAMEBUF_DISPLAY display_framebuf.c)
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zephyr_sources_ifdef(CONFIG_FRAMEBUF_DISPLAY display_framebuf.c)
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zephyr_sources_ifdef(CONFIG_ILI9340 display_ili9340.c)
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zephyr_sources_ifdef(CONFIG_ILI9340 display_ili9340.c)
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zephyr_sources_ifdef(CONFIG_ST7789V display_st7789v.c)
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zephyr_sources_ifdef(CONFIG_ST7789V display_st7789v.c)
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zephyr_sources_ifdef(CONFIG_GD7965 gd7965.c)
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zephyr_sources_ifdef(CONFIG_MICROBIT_DISPLAY
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zephyr_sources_ifdef(CONFIG_MICROBIT_DISPLAY
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mb_display.c
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mb_display.c
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@ -22,6 +22,7 @@ source "drivers/display/Kconfig.sdl"
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source "drivers/display/Kconfig.ssd1306"
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source "drivers/display/Kconfig.ssd1306"
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source "drivers/display/Kconfig.ssd16xx"
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source "drivers/display/Kconfig.ssd16xx"
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source "drivers/display/Kconfig.st7789v"
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source "drivers/display/Kconfig.st7789v"
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source "drivers/display/Kconfig.gd7965"
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source "drivers/display/Kconfig.dummy"
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source "drivers/display/Kconfig.dummy"
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config FRAMEBUF_DISPLAY
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config FRAMEBUF_DISPLAY
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11
drivers/display/Kconfig.gd7965
Normal file
11
drivers/display/Kconfig.gd7965
Normal file
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@ -0,0 +1,11 @@
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# GD7965 display controller configuration options
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# Copyright (c) 2020 Phytec Messtechnik GmbH
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# SPDX-License-Identifier: Apache-2.0
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config GD7965
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bool "GD7965 compatible display controller driver"
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depends on SPI
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depends on HEAP_MEM_POOL_SIZE != 0
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help
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Enable driver for GD7965 compatible controller.
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464
drivers/display/gd7965.c
Normal file
464
drivers/display/gd7965.c
Normal file
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@ -0,0 +1,464 @@
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/*
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* Copyright (c) 2020 PHYTEC Messtechnik GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <device.h>
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#include <init.h>
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#include <drivers/display.h>
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#include <drivers/gpio.h>
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#include <drivers/spi.h>
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#include <sys/byteorder.h>
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#include "gd7965_regs.h"
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#include <logging/log.h>
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LOG_MODULE_REGISTER(gd7965, CONFIG_DISPLAY_LOG_LEVEL);
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/**
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* GD7965 compatible EPD controller driver.
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*
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* Currently only the black/white pannels are supported (KW mode),
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* also first gate/source should be 0.
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*/
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#define GD7965_SPI_FREQ DT_INST_0_GOODDISPLAY_GD7965_SPI_MAX_FREQUENCY
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#define GD7965_BUS_NAME DT_INST_0_GOODDISPLAY_GD7965_BUS_NAME
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#define GD7965_DC_PIN DT_INST_0_GOODDISPLAY_GD7965_DC_GPIOS_PIN
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#define GD7965_DC_CNTRL DT_INST_0_GOODDISPLAY_GD7965_DC_GPIOS_CONTROLLER
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#define GD7965_CS_PIN DT_INST_0_GOODDISPLAY_GD7965_CS_GPIOS_PIN
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#if defined(DT_INST_0_GOODDISPLAY_GD7965_CS_GPIOS_CONTROLLER)
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#define GD7965_CS_CNTRL DT_INST_0_GOODDISPLAY_GD7965_CS_GPIOS_CONTROLLER
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#endif
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#define GD7965_BUSY_PIN DT_INST_0_GOODDISPLAY_GD7965_BUSY_GPIOS_PIN
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#define GD7965_BUSY_CNTRL DT_INST_0_GOODDISPLAY_GD7965_BUSY_GPIOS_CONTROLLER
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#define GD7965_RESET_PIN DT_INST_0_GOODDISPLAY_GD7965_RESET_GPIOS_PIN
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#define GD7965_RESET_CNTRL DT_INST_0_GOODDISPLAY_GD7965_RESET_GPIOS_CONTROLLER
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#define EPD_PANEL_WIDTH DT_INST_0_GOODDISPLAY_GD7965_WIDTH
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#define EPD_PANEL_HEIGHT DT_INST_0_GOODDISPLAY_GD7965_HEIGHT
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#define GD7965_PIXELS_PER_BYTE 8U
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/* Horizontally aligned page! */
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#define GD7965_NUMOF_PAGES (EPD_PANEL_WIDTH / \
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GD7965_PIXELS_PER_BYTE)
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#define GD7965_PANEL_FIRST_GATE 0U
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#define GD7965_PANEL_LAST_GATE (EPD_PANEL_HEIGHT - 1)
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#define GD7965_PANEL_FIRST_PAGE 0U
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#define GD7965_PANEL_LAST_PAGE (GD7965_NUMOF_PAGES - 1)
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struct gd7965_data {
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struct device *reset;
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struct device *dc;
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struct device *busy;
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struct device *spi_dev;
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struct spi_config spi_config;
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#if defined(GD7965_CS_CNTRL)
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struct spi_cs_control cs_ctrl;
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#endif
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};
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static u8_t gd7965_softstart[] = DT_INST_0_GOODDISPLAY_GD7965_SOFTSTART;
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static u8_t gd7965_pwr[] = DT_INST_0_GOODDISPLAY_GD7965_PWR;
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/* Border and data polarity settings */
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static u8_t bdd_polarity;
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static bool blanking_on = true;
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static inline int gd7965_write_cmd(struct gd7965_data *driver,
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u8_t cmd, u8_t *data, size_t len)
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{
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struct spi_buf buf = {.buf = &cmd, .len = sizeof(cmd)};
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struct spi_buf_set buf_set = {.buffers = &buf, .count = 1};
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gpio_pin_write(driver->dc, GD7965_DC_PIN, 0);
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if (spi_write(driver->spi_dev, &driver->spi_config, &buf_set)) {
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return -EIO;
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}
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if (data != NULL) {
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buf.buf = data;
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buf.len = len;
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gpio_pin_write(driver->dc, GD7965_DC_PIN, 1);
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if (spi_write(driver->spi_dev, &driver->spi_config, &buf_set)) {
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return -EIO;
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}
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}
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return 0;
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}
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static inline void gd7965_busy_wait(struct gd7965_data *driver)
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{
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u32_t val = 0U;
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gpio_pin_read(driver->busy, GD7965_BUSY_PIN, &val);
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while (val == 0) {
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k_sleep(GD7965_BUSY_DELAY);
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gpio_pin_read(driver->busy, GD7965_BUSY_PIN, &val);
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}
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}
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static int gd7965_update_display(const struct device *dev)
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{
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struct gd7965_data *driver = dev->driver_data;
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LOG_DBG("Trigger update sequence");
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if (gd7965_write_cmd(driver, GD7965_CMD_DRF, NULL, 0)) {
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return -EIO;
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}
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k_sleep(GD7965_BUSY_DELAY);
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return 0;
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}
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static int gd7965_blanking_off(const struct device *dev)
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{
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struct gd7965_data *driver = dev->driver_data;
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if (blanking_on) {
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/* Update EPD pannel in normal mode */
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gd7965_busy_wait(driver);
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if (gd7965_update_display(dev)) {
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return -EIO;
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}
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}
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blanking_on = false;
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return 0;
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}
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static int gd7965_blanking_on(const struct device *dev)
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{
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blanking_on = true;
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return 0;
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}
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static int gd7965_write(const struct device *dev, const u16_t x, const u16_t y,
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const struct display_buffer_descriptor *desc,
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const void *buf)
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{
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struct gd7965_data *driver = dev->driver_data;
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u16_t x_end_idx = x + desc->width - 1;
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u16_t y_end_idx = y + desc->height - 1;
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u8_t ptl[GD7965_PTL_REG_LENGTH] = {0};
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size_t buf_len;
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LOG_DBG("x %u, y %u, height %u, width %u, pitch %u",
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x, y, desc->height, desc->width, desc->pitch);
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buf_len = MIN(desc->buf_size,
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desc->height * desc->width / GD7965_PIXELS_PER_BYTE);
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__ASSERT(desc->width <= desc->pitch, "Pitch is smaller then width");
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__ASSERT(buf != NULL, "Buffer is not available");
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__ASSERT(buf_len != 0U, "Buffer of length zero");
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__ASSERT(!(desc->width % GD7965_PIXELS_PER_BYTE),
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"Buffer width not multiple of %d", GD7965_PIXELS_PER_BYTE);
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if ((y_end_idx > (EPD_PANEL_HEIGHT - 1)) ||
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(x_end_idx > (EPD_PANEL_WIDTH - 1))) {
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LOG_ERR("Position out of bounds");
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return -EINVAL;
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}
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/* Setup Partial Window and enable Partial Mode */
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sys_put_be16(x, &ptl[GD7965_PTL_HRST_IDX]);
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sys_put_be16(x_end_idx, &ptl[GD7965_PTL_HRED_IDX]);
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sys_put_be16(y, &ptl[GD7965_PTL_VRST_IDX]);
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sys_put_be16(y_end_idx, &ptl[GD7965_PTL_VRED_IDX]);
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ptl[sizeof(ptl) - 1] = GD7965_PTL_PT_SCAN;
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LOG_HEXDUMP_DBG(ptl, sizeof(ptl), "ptl");
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gd7965_busy_wait(driver);
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if (gd7965_write_cmd(driver, GD7965_CMD_PTIN, NULL, 0)) {
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return -EIO;
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}
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if (gd7965_write_cmd(driver, GD7965_CMD_PTL, ptl, sizeof(ptl))) {
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return -EIO;
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}
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/* Disable boarder output */
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bdd_polarity |= GD7965_CDI_BDZ;
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if (gd7965_write_cmd(driver, GD7965_CMD_CDI,
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&bdd_polarity, sizeof(bdd_polarity))) {
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return -EIO;
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}
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if (gd7965_write_cmd(driver, GD7965_CMD_DTM2, (u8_t *)buf, buf_len)) {
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return -EIO;
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}
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/* Update partial window and disable Partial Mode */
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if (blanking_on == false) {
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if (gd7965_update_display(dev)) {
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return -EIO;
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}
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}
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/* Enable boarder output */
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bdd_polarity &= ~GD7965_CDI_BDZ;
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if (gd7965_write_cmd(driver, GD7965_CMD_CDI,
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&bdd_polarity, sizeof(bdd_polarity))) {
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return -EIO;
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}
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if (gd7965_write_cmd(driver, GD7965_CMD_PTOUT, NULL, 0)) {
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return -EIO;
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}
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return 0;
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}
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static int gd7965_read(const struct device *dev, const u16_t x, const u16_t y,
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const struct display_buffer_descriptor *desc, void *buf)
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{
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LOG_ERR("not supported");
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return -ENOTSUP;
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}
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static void *gd7965_get_framebuffer(const struct device *dev)
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{
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LOG_ERR("not supported");
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return NULL;
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}
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static int gd7965_set_brightness(const struct device *dev,
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const u8_t brightness)
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{
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LOG_WRN("not supported");
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return -ENOTSUP;
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}
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static int gd7965_set_contrast(const struct device *dev, u8_t contrast)
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{
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LOG_WRN("not supported");
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return -ENOTSUP;
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}
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static void gd7965_get_capabilities(const struct device *dev,
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struct display_capabilities *caps)
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{
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memset(caps, 0, sizeof(struct display_capabilities));
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caps->x_resolution = EPD_PANEL_WIDTH;
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caps->y_resolution = EPD_PANEL_HEIGHT;
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caps->supported_pixel_formats = PIXEL_FORMAT_MONO10;
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caps->current_pixel_format = PIXEL_FORMAT_MONO10;
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caps->screen_info = SCREEN_INFO_MONO_MSB_FIRST | SCREEN_INFO_EPD;
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}
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static int gd7965_set_orientation(const struct device *dev,
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const enum display_orientation
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orientation)
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{
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LOG_ERR("Unsupported");
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return -ENOTSUP;
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}
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static int gd7965_set_pixel_format(const struct device *dev,
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const enum display_pixel_format pf)
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{
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if (pf == PIXEL_FORMAT_MONO10) {
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return 0;
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}
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LOG_ERR("not supported");
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return -ENOTSUP;
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}
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static int gd7965_clear_and_write_buffer(struct device *dev,
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u8_t pattern, bool update)
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{
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struct display_buffer_descriptor desc = {
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.buf_size = GD7965_NUMOF_PAGES,
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.width = EPD_PANEL_WIDTH,
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.height = 1,
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.pitch = EPD_PANEL_WIDTH,
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};
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u8_t *line;
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line = k_malloc(GD7965_NUMOF_PAGES);
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if (line == NULL) {
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return -ENOMEM;
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}
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memset(line, pattern, GD7965_NUMOF_PAGES);
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for (int i = 0; i < EPD_PANEL_HEIGHT; i++) {
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gd7965_write(dev, 0, i, &desc, line);
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}
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k_free(line);
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if (update == true) {
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if (gd7965_update_display(dev)) {
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return -EIO;
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}
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}
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return 0;
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}
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static int gd7965_controller_init(struct device *dev)
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{
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struct gd7965_data *driver = dev->driver_data;
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u8_t tmp[GD7965_TRES_REG_LENGTH];
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gpio_pin_write(driver->reset, GD7965_RESET_PIN, 0);
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k_sleep(GD7965_RESET_DELAY);
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gpio_pin_write(driver->reset, GD7965_RESET_PIN, 1);
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k_sleep(GD7965_RESET_DELAY);
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gd7965_busy_wait(driver);
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LOG_DBG("Initialize GD7965 controller");
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||||||
|
if (gd7965_write_cmd(driver, GD7965_CMD_PWR, gd7965_pwr,
|
||||||
|
sizeof(gd7965_pwr))) {
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (gd7965_write_cmd(driver, GD7965_CMD_BTST,
|
||||||
|
gd7965_softstart, sizeof(gd7965_softstart))) {
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Turn on: booster, controller, regulators, and sensor. */
|
||||||
|
if (gd7965_write_cmd(driver, GD7965_CMD_PON, NULL, 0)) {
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
k_sleep(GD7965_PON_DELAY);
|
||||||
|
gd7965_busy_wait(driver);
|
||||||
|
|
||||||
|
/* Pannel settings, KW mode */
|
||||||
|
tmp[0] = GD7965_PSR_KW_R |
|
||||||
|
GD7965_PSR_UD |
|
||||||
|
GD7965_PSR_SHL |
|
||||||
|
GD7965_PSR_SHD |
|
||||||
|
GD7965_PSR_RST;
|
||||||
|
if (gd7965_write_cmd(driver, GD7965_CMD_PSR, tmp, 1)) {
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set panel resolution */
|
||||||
|
sys_put_be16(EPD_PANEL_WIDTH, &tmp[GD7965_TRES_HRES_IDX]);
|
||||||
|
sys_put_be16(EPD_PANEL_HEIGHT, &tmp[GD7965_TRES_VRES_IDX]);
|
||||||
|
LOG_HEXDUMP_DBG(tmp, sizeof(tmp), "TRES");
|
||||||
|
if (gd7965_write_cmd(driver, GD7965_CMD_TRES,
|
||||||
|
tmp, GD7965_TRES_REG_LENGTH)) {
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
bdd_polarity = GD7965_CDI_BDV1 |
|
||||||
|
GD7965_CDI_N2OCP | GD7965_CDI_DDX0;
|
||||||
|
tmp[GD7965_CDI_BDZ_DDX_IDX] = bdd_polarity;
|
||||||
|
tmp[GD7965_CDI_CDI_IDX] = DT_INST_0_GOODDISPLAY_GD7965_CDI;
|
||||||
|
LOG_HEXDUMP_DBG(tmp, GD7965_CDI_REG_LENGTH, "CDI");
|
||||||
|
if (gd7965_write_cmd(driver, GD7965_CMD_CDI, tmp,
|
||||||
|
GD7965_CDI_REG_LENGTH)) {
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
tmp[0] = DT_INST_0_GOODDISPLAY_GD7965_TCON;
|
||||||
|
if (gd7965_write_cmd(driver, GD7965_CMD_TCON, tmp, 1)) {
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable Auto Sequence */
|
||||||
|
tmp[0] = GD7965_AUTO_PON_DRF_POF;
|
||||||
|
if (gd7965_write_cmd(driver, GD7965_CMD_AUTO, tmp, 1)) {
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (gd7965_clear_and_write_buffer(dev, 0xff, false)) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int gd7965_init(struct device *dev)
|
||||||
|
{
|
||||||
|
struct gd7965_data *driver = dev->driver_data;
|
||||||
|
|
||||||
|
LOG_DBG("");
|
||||||
|
|
||||||
|
driver->spi_dev = device_get_binding(GD7965_BUS_NAME);
|
||||||
|
if (driver->spi_dev == NULL) {
|
||||||
|
LOG_ERR("Could not get SPI device for GD7965");
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
driver->spi_config.frequency = GD7965_SPI_FREQ;
|
||||||
|
driver->spi_config.operation = SPI_OP_MODE_MASTER | SPI_WORD_SET(8);
|
||||||
|
driver->spi_config.slave = DT_INST_0_GOODDISPLAY_GD7965_BASE_ADDRESS;
|
||||||
|
driver->spi_config.cs = NULL;
|
||||||
|
|
||||||
|
driver->reset = device_get_binding(GD7965_RESET_CNTRL);
|
||||||
|
if (driver->reset == NULL) {
|
||||||
|
LOG_ERR("Could not get GPIO port for GD7965 reset");
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
gpio_pin_configure(driver->reset, GD7965_RESET_PIN,
|
||||||
|
GPIO_DIR_OUT);
|
||||||
|
|
||||||
|
driver->dc = device_get_binding(GD7965_DC_CNTRL);
|
||||||
|
if (driver->dc == NULL) {
|
||||||
|
LOG_ERR("Could not get GPIO port for GD7965 DC signal");
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
gpio_pin_configure(driver->dc, GD7965_DC_PIN,
|
||||||
|
GPIO_DIR_OUT);
|
||||||
|
|
||||||
|
driver->busy = device_get_binding(GD7965_BUSY_CNTRL);
|
||||||
|
if (driver->busy == NULL) {
|
||||||
|
LOG_ERR("Could not get GPIO port for GD7965 busy signal");
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
gpio_pin_configure(driver->busy, GD7965_BUSY_PIN,
|
||||||
|
GPIO_DIR_IN);
|
||||||
|
|
||||||
|
#if defined(GD7965_CS_CNTRL)
|
||||||
|
driver->cs_ctrl.gpio_dev = device_get_binding(GD7965_CS_CNTRL);
|
||||||
|
if (!driver->cs_ctrl.gpio_dev) {
|
||||||
|
LOG_ERR("Unable to get SPI GPIO CS device");
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
driver->cs_ctrl.gpio_pin = GD7965_CS_PIN;
|
||||||
|
driver->cs_ctrl.delay = 0U;
|
||||||
|
driver->spi_config.cs = &driver->cs_ctrl;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return gd7965_controller_init(dev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct gd7965_data gd7965_driver;
|
||||||
|
|
||||||
|
static struct display_driver_api gd7965_driver_api = {
|
||||||
|
.blanking_on = gd7965_blanking_on,
|
||||||
|
.blanking_off = gd7965_blanking_off,
|
||||||
|
.write = gd7965_write,
|
||||||
|
.read = gd7965_read,
|
||||||
|
.get_framebuffer = gd7965_get_framebuffer,
|
||||||
|
.set_brightness = gd7965_set_brightness,
|
||||||
|
.set_contrast = gd7965_set_contrast,
|
||||||
|
.get_capabilities = gd7965_get_capabilities,
|
||||||
|
.set_pixel_format = gd7965_set_pixel_format,
|
||||||
|
.set_orientation = gd7965_set_orientation,
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
DEVICE_AND_API_INIT(gd7965, DT_INST_0_GOODDISPLAY_GD7965_LABEL, gd7965_init,
|
||||||
|
&gd7965_driver, NULL,
|
||||||
|
POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY,
|
||||||
|
&gd7965_driver_api);
|
||||||
91
drivers/display/gd7965_regs.h
Normal file
91
drivers/display/gd7965_regs.h
Normal file
|
|
@ -0,0 +1,91 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2020 PHYTEC Messtechnik GmbH
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef ZEPHYR_DRIVERS_DISPLAY_GD7965_REGS_H_
|
||||||
|
#define ZEPHYR_DRIVERS_DISPLAY_GD7965_REGS_H_
|
||||||
|
|
||||||
|
#define GD7965_CMD_PSR 0x00
|
||||||
|
#define GD7965_CMD_PWR 0x01
|
||||||
|
#define GD7965_CMD_POF 0x02
|
||||||
|
#define GD7965_CMD_PFS 0x03
|
||||||
|
#define GD7965_CMD_PON 0x04
|
||||||
|
#define GD7965_CMD_PMES 0x05
|
||||||
|
#define GD7965_CMD_BTST 0x06
|
||||||
|
#define GD7965_CMD_DSLP 0x07
|
||||||
|
#define GD7965_CMD_DTM1 0x10
|
||||||
|
#define GD7965_CMD_DSP 0x11
|
||||||
|
#define GD7965_CMD_DRF 0x12
|
||||||
|
#define GD7965_CMD_DTM2 0x13
|
||||||
|
#define GD7965_CMD_DUSPI 0x15
|
||||||
|
#define GD7965_CMD_AUTO 0x17
|
||||||
|
#define GD7965_CMD_LUTOPT 0x2A
|
||||||
|
#define GD7965_CMD_KWOPT 0x2B
|
||||||
|
#define GD7965_CMD_PLL 0x30
|
||||||
|
#define GD7965_CMD_TSC 0x40
|
||||||
|
#define GD7965_CMD_TSE 0x41
|
||||||
|
#define GD7965_CMD_TSW 0x42
|
||||||
|
#define GD7965_CMD_TSR 0x43
|
||||||
|
#define GD7965_CMD_PBC 0x44
|
||||||
|
#define GD7965_CMD_CDI 0x50
|
||||||
|
#define GD7965_CMD_LPD 0x51
|
||||||
|
#define GD7965_CMD_EVS 0x52
|
||||||
|
#define GD7965_CMD_TCON 0x60
|
||||||
|
#define GD7965_CMD_TRES 0x61
|
||||||
|
#define GD7965_CMD_GSST 0x65
|
||||||
|
#define GD7965_CMD_REV 0x70
|
||||||
|
#define GD7965_CMD_FLG 0x71
|
||||||
|
#define GD7965_CMD_AMV 0x80
|
||||||
|
#define GD7965_CMD_VV 0x81
|
||||||
|
#define GD7965_CMD_VDCS 0x82
|
||||||
|
#define GD7965_CMD_PTL 0x90
|
||||||
|
#define GD7965_CMD_PTIN 0x91
|
||||||
|
#define GD7965_CMD_PTOUT 0x92
|
||||||
|
#define GD7965_CMD_PGM 0xA0
|
||||||
|
#define GD7965_CMD_APG 0xA1
|
||||||
|
#define GD7965_CMD_ROTP 0xA2
|
||||||
|
#define GD7965_CMD_CCSET 0xE0
|
||||||
|
#define GD7965_CMD_PWS 0xE3
|
||||||
|
#define GD7965_CMD_LVSEL 0xE4
|
||||||
|
#define GD7965_CMD_TSSET 0xE5
|
||||||
|
#define GD7965_CMD_TSBDRY 0xE7
|
||||||
|
|
||||||
|
#define GD7965_PSR_REG BIT(5)
|
||||||
|
#define GD7965_PSR_KW_R BIT(4)
|
||||||
|
#define GD7965_PSR_UD BIT(3)
|
||||||
|
#define GD7965_PSR_SHL BIT(2)
|
||||||
|
#define GD7965_PSR_SHD BIT(1)
|
||||||
|
#define GD7965_PSR_RST BIT(0)
|
||||||
|
|
||||||
|
#define GD7965_AUTO_PON_DRF_POF 0xA5
|
||||||
|
#define GD7965_AUTO_PON_DRF_POF_DSLP 0xA7
|
||||||
|
|
||||||
|
#define GD7965_CDI_REG_LENGTH 2U
|
||||||
|
#define GD7965_CDI_BDZ_DDX_IDX 0
|
||||||
|
#define GD7965_CDI_CDI_IDX 1
|
||||||
|
#define GD7965_CDI_BDZ BIT(7)
|
||||||
|
#define GD7965_CDI_BDV1 BIT(5)
|
||||||
|
#define GD7965_CDI_BDV0 BIT(4)
|
||||||
|
#define GD7965_CDI_N2OCP BIT(3)
|
||||||
|
#define GD7965_CDI_DDX1 BIT(1)
|
||||||
|
#define GD7965_CDI_DDX0 BIT(0)
|
||||||
|
|
||||||
|
#define GD7965_TRES_REG_LENGTH 4U
|
||||||
|
#define GD7965_TRES_HRES_IDX 0
|
||||||
|
#define GD7965_TRES_VRES_IDX 2
|
||||||
|
|
||||||
|
#define GD7965_PTL_REG_LENGTH 9U
|
||||||
|
#define GD7965_PTL_HRST_IDX 0
|
||||||
|
#define GD7965_PTL_HRED_IDX 2
|
||||||
|
#define GD7965_PTL_VRST_IDX 4
|
||||||
|
#define GD7965_PTL_VRED_IDX 6
|
||||||
|
#define GD7965_PTL_PT_SCAN BIT(0)
|
||||||
|
|
||||||
|
/* Time constants in ms */
|
||||||
|
#define GD7965_RESET_DELAY 10U
|
||||||
|
#define GD7965_PON_DELAY 100U
|
||||||
|
#define GD7965_BUSY_DELAY 1U
|
||||||
|
|
||||||
|
#endif /* ZEPHYR_DRIVERS_DISPLAY_GD7965_REGS_H_ */
|
||||||
51
dts/bindings/display/gooddisplay,gd7965.yaml
Normal file
51
dts/bindings/display/gooddisplay,gd7965.yaml
Normal file
|
|
@ -0,0 +1,51 @@
|
||||||
|
# Copyright (c) 2020, Phytec Messtechnik GmbH
|
||||||
|
# SPDX-License-Identifier: Apache-2.0
|
||||||
|
|
||||||
|
description: GD7965 EPD display controller
|
||||||
|
|
||||||
|
compatible: "gooddisplay,gd7965"
|
||||||
|
|
||||||
|
include: spi-device.yaml
|
||||||
|
|
||||||
|
properties:
|
||||||
|
height:
|
||||||
|
type: int
|
||||||
|
required: true
|
||||||
|
description: Height in pixel of the panel driven by the controller
|
||||||
|
|
||||||
|
width:
|
||||||
|
type: int
|
||||||
|
required: true
|
||||||
|
description: Width in pixel of the panel driven by the controller
|
||||||
|
|
||||||
|
reset-gpios:
|
||||||
|
type: phandle-array
|
||||||
|
required: true
|
||||||
|
|
||||||
|
dc-gpios:
|
||||||
|
type: phandle-array
|
||||||
|
required: true
|
||||||
|
|
||||||
|
busy-gpios:
|
||||||
|
type: phandle-array
|
||||||
|
required: true
|
||||||
|
|
||||||
|
pwr:
|
||||||
|
type: uint8-array
|
||||||
|
required: true
|
||||||
|
description: Power Setting (PWR) values
|
||||||
|
|
||||||
|
softstart:
|
||||||
|
type: uint8-array
|
||||||
|
required: true
|
||||||
|
description: Booster Soft Start (BTST) values
|
||||||
|
|
||||||
|
cdi:
|
||||||
|
type: int
|
||||||
|
required: true
|
||||||
|
description: VCOM and data interval value
|
||||||
|
|
||||||
|
tcon:
|
||||||
|
type: int
|
||||||
|
required: true
|
||||||
|
description: TCON setting value
|
||||||
Loading…
Add table
Add a link
Reference in a new issue