From c68ac431cc4d5ee43a93f2c230da5a7b5688ff8f Mon Sep 17 00:00:00 2001 From: Johann Fischer Date: Tue, 14 Jan 2020 23:53:10 +0100 Subject: [PATCH] drivers: display: add support for GD7965 display controller Add support for GD7965 display controller. Signed-off-by: Johann Fischer --- drivers/display/CMakeLists.txt | 1 + drivers/display/Kconfig | 1 + drivers/display/Kconfig.gd7965 | 11 + drivers/display/gd7965.c | 464 +++++++++++++++++++ drivers/display/gd7965_regs.h | 91 ++++ dts/bindings/display/gooddisplay,gd7965.yaml | 51 ++ 6 files changed, 619 insertions(+) create mode 100644 drivers/display/Kconfig.gd7965 create mode 100644 drivers/display/gd7965.c create mode 100644 drivers/display/gd7965_regs.h create mode 100644 dts/bindings/display/gooddisplay,gd7965.yaml diff --git a/drivers/display/CMakeLists.txt b/drivers/display/CMakeLists.txt index c1db6b31836..9a6542c59f4 100644 --- a/drivers/display/CMakeLists.txt +++ b/drivers/display/CMakeLists.txt @@ -9,6 +9,7 @@ zephyr_sources_ifdef(CONFIG_DUMMY_DISPLAY display_dummy.c) zephyr_sources_ifdef(CONFIG_FRAMEBUF_DISPLAY display_framebuf.c) zephyr_sources_ifdef(CONFIG_ILI9340 display_ili9340.c) zephyr_sources_ifdef(CONFIG_ST7789V display_st7789v.c) +zephyr_sources_ifdef(CONFIG_GD7965 gd7965.c) zephyr_sources_ifdef(CONFIG_MICROBIT_DISPLAY mb_display.c diff --git a/drivers/display/Kconfig b/drivers/display/Kconfig index ba4dd9d5167..7767fa018c4 100644 --- a/drivers/display/Kconfig +++ b/drivers/display/Kconfig @@ -22,6 +22,7 @@ source "drivers/display/Kconfig.sdl" source "drivers/display/Kconfig.ssd1306" source "drivers/display/Kconfig.ssd16xx" source "drivers/display/Kconfig.st7789v" +source "drivers/display/Kconfig.gd7965" source "drivers/display/Kconfig.dummy" config FRAMEBUF_DISPLAY diff --git a/drivers/display/Kconfig.gd7965 b/drivers/display/Kconfig.gd7965 new file mode 100644 index 00000000000..9c4c2e84b6a --- /dev/null +++ b/drivers/display/Kconfig.gd7965 @@ -0,0 +1,11 @@ +# GD7965 display controller configuration options + +# Copyright (c) 2020 Phytec Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +config GD7965 + bool "GD7965 compatible display controller driver" + depends on SPI + depends on HEAP_MEM_POOL_SIZE != 0 + help + Enable driver for GD7965 compatible controller. diff --git a/drivers/display/gd7965.c b/drivers/display/gd7965.c new file mode 100644 index 00000000000..e24f79cda6d --- /dev/null +++ b/drivers/display/gd7965.c @@ -0,0 +1,464 @@ +/* + * Copyright (c) 2020 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "gd7965_regs.h" + +#include +LOG_MODULE_REGISTER(gd7965, CONFIG_DISPLAY_LOG_LEVEL); + +/** + * GD7965 compatible EPD controller driver. + * + * Currently only the black/white pannels are supported (KW mode), + * also first gate/source should be 0. + */ + +#define GD7965_SPI_FREQ DT_INST_0_GOODDISPLAY_GD7965_SPI_MAX_FREQUENCY +#define GD7965_BUS_NAME DT_INST_0_GOODDISPLAY_GD7965_BUS_NAME +#define GD7965_DC_PIN DT_INST_0_GOODDISPLAY_GD7965_DC_GPIOS_PIN +#define GD7965_DC_CNTRL DT_INST_0_GOODDISPLAY_GD7965_DC_GPIOS_CONTROLLER +#define GD7965_CS_PIN DT_INST_0_GOODDISPLAY_GD7965_CS_GPIOS_PIN +#if defined(DT_INST_0_GOODDISPLAY_GD7965_CS_GPIOS_CONTROLLER) +#define GD7965_CS_CNTRL DT_INST_0_GOODDISPLAY_GD7965_CS_GPIOS_CONTROLLER +#endif +#define GD7965_BUSY_PIN DT_INST_0_GOODDISPLAY_GD7965_BUSY_GPIOS_PIN +#define GD7965_BUSY_CNTRL DT_INST_0_GOODDISPLAY_GD7965_BUSY_GPIOS_CONTROLLER +#define GD7965_RESET_PIN DT_INST_0_GOODDISPLAY_GD7965_RESET_GPIOS_PIN +#define GD7965_RESET_CNTRL DT_INST_0_GOODDISPLAY_GD7965_RESET_GPIOS_CONTROLLER + +#define EPD_PANEL_WIDTH DT_INST_0_GOODDISPLAY_GD7965_WIDTH +#define EPD_PANEL_HEIGHT DT_INST_0_GOODDISPLAY_GD7965_HEIGHT +#define GD7965_PIXELS_PER_BYTE 8U + +/* Horizontally aligned page! */ +#define GD7965_NUMOF_PAGES (EPD_PANEL_WIDTH / \ + GD7965_PIXELS_PER_BYTE) +#define GD7965_PANEL_FIRST_GATE 0U +#define GD7965_PANEL_LAST_GATE (EPD_PANEL_HEIGHT - 1) +#define GD7965_PANEL_FIRST_PAGE 0U +#define GD7965_PANEL_LAST_PAGE (GD7965_NUMOF_PAGES - 1) + + +struct gd7965_data { + struct device *reset; + struct device *dc; + struct device *busy; + struct device *spi_dev; + struct spi_config spi_config; +#if defined(GD7965_CS_CNTRL) + struct spi_cs_control cs_ctrl; +#endif +}; + +static u8_t gd7965_softstart[] = DT_INST_0_GOODDISPLAY_GD7965_SOFTSTART; +static u8_t gd7965_pwr[] = DT_INST_0_GOODDISPLAY_GD7965_PWR; + +/* Border and data polarity settings */ +static u8_t bdd_polarity; + +static bool blanking_on = true; + +static inline int gd7965_write_cmd(struct gd7965_data *driver, + u8_t cmd, u8_t *data, size_t len) +{ + struct spi_buf buf = {.buf = &cmd, .len = sizeof(cmd)}; + struct spi_buf_set buf_set = {.buffers = &buf, .count = 1}; + + gpio_pin_write(driver->dc, GD7965_DC_PIN, 0); + if (spi_write(driver->spi_dev, &driver->spi_config, &buf_set)) { + return -EIO; + } + + if (data != NULL) { + buf.buf = data; + buf.len = len; + gpio_pin_write(driver->dc, GD7965_DC_PIN, 1); + if (spi_write(driver->spi_dev, &driver->spi_config, &buf_set)) { + return -EIO; + } + } + + return 0; +} + +static inline void gd7965_busy_wait(struct gd7965_data *driver) +{ + u32_t val = 0U; + + gpio_pin_read(driver->busy, GD7965_BUSY_PIN, &val); + while (val == 0) { + k_sleep(GD7965_BUSY_DELAY); + gpio_pin_read(driver->busy, GD7965_BUSY_PIN, &val); + } +} + +static int gd7965_update_display(const struct device *dev) +{ + struct gd7965_data *driver = dev->driver_data; + + LOG_DBG("Trigger update sequence"); + if (gd7965_write_cmd(driver, GD7965_CMD_DRF, NULL, 0)) { + return -EIO; + } + + k_sleep(GD7965_BUSY_DELAY); + + return 0; +} + +static int gd7965_blanking_off(const struct device *dev) +{ + struct gd7965_data *driver = dev->driver_data; + + if (blanking_on) { + /* Update EPD pannel in normal mode */ + gd7965_busy_wait(driver); + if (gd7965_update_display(dev)) { + return -EIO; + } + } + + blanking_on = false; + + return 0; +} + +static int gd7965_blanking_on(const struct device *dev) +{ + blanking_on = true; + + return 0; +} + +static int gd7965_write(const struct device *dev, const u16_t x, const u16_t y, + const struct display_buffer_descriptor *desc, + const void *buf) +{ + struct gd7965_data *driver = dev->driver_data; + u16_t x_end_idx = x + desc->width - 1; + u16_t y_end_idx = y + desc->height - 1; + u8_t ptl[GD7965_PTL_REG_LENGTH] = {0}; + size_t buf_len; + + LOG_DBG("x %u, y %u, height %u, width %u, pitch %u", + x, y, desc->height, desc->width, desc->pitch); + + buf_len = MIN(desc->buf_size, + desc->height * desc->width / GD7965_PIXELS_PER_BYTE); + __ASSERT(desc->width <= desc->pitch, "Pitch is smaller then width"); + __ASSERT(buf != NULL, "Buffer is not available"); + __ASSERT(buf_len != 0U, "Buffer of length zero"); + __ASSERT(!(desc->width % GD7965_PIXELS_PER_BYTE), + "Buffer width not multiple of %d", GD7965_PIXELS_PER_BYTE); + + if ((y_end_idx > (EPD_PANEL_HEIGHT - 1)) || + (x_end_idx > (EPD_PANEL_WIDTH - 1))) { + LOG_ERR("Position out of bounds"); + return -EINVAL; + } + + /* Setup Partial Window and enable Partial Mode */ + sys_put_be16(x, &ptl[GD7965_PTL_HRST_IDX]); + sys_put_be16(x_end_idx, &ptl[GD7965_PTL_HRED_IDX]); + sys_put_be16(y, &ptl[GD7965_PTL_VRST_IDX]); + sys_put_be16(y_end_idx, &ptl[GD7965_PTL_VRED_IDX]); + ptl[sizeof(ptl) - 1] = GD7965_PTL_PT_SCAN; + LOG_HEXDUMP_DBG(ptl, sizeof(ptl), "ptl"); + + gd7965_busy_wait(driver); + if (gd7965_write_cmd(driver, GD7965_CMD_PTIN, NULL, 0)) { + return -EIO; + } + + if (gd7965_write_cmd(driver, GD7965_CMD_PTL, ptl, sizeof(ptl))) { + return -EIO; + } + + /* Disable boarder output */ + bdd_polarity |= GD7965_CDI_BDZ; + if (gd7965_write_cmd(driver, GD7965_CMD_CDI, + &bdd_polarity, sizeof(bdd_polarity))) { + return -EIO; + } + + if (gd7965_write_cmd(driver, GD7965_CMD_DTM2, (u8_t *)buf, buf_len)) { + return -EIO; + } + + /* Update partial window and disable Partial Mode */ + if (blanking_on == false) { + if (gd7965_update_display(dev)) { + return -EIO; + } + } + + /* Enable boarder output */ + bdd_polarity &= ~GD7965_CDI_BDZ; + if (gd7965_write_cmd(driver, GD7965_CMD_CDI, + &bdd_polarity, sizeof(bdd_polarity))) { + return -EIO; + } + + if (gd7965_write_cmd(driver, GD7965_CMD_PTOUT, NULL, 0)) { + return -EIO; + } + + return 0; +} + +static int gd7965_read(const struct device *dev, const u16_t x, const u16_t y, + const struct display_buffer_descriptor *desc, void *buf) +{ + LOG_ERR("not supported"); + return -ENOTSUP; +} + +static void *gd7965_get_framebuffer(const struct device *dev) +{ + LOG_ERR("not supported"); + return NULL; +} + +static int gd7965_set_brightness(const struct device *dev, + const u8_t brightness) +{ + LOG_WRN("not supported"); + return -ENOTSUP; +} + +static int gd7965_set_contrast(const struct device *dev, u8_t contrast) +{ + LOG_WRN("not supported"); + return -ENOTSUP; +} + +static void gd7965_get_capabilities(const struct device *dev, + struct display_capabilities *caps) +{ + memset(caps, 0, sizeof(struct display_capabilities)); + caps->x_resolution = EPD_PANEL_WIDTH; + caps->y_resolution = EPD_PANEL_HEIGHT; + caps->supported_pixel_formats = PIXEL_FORMAT_MONO10; + caps->current_pixel_format = PIXEL_FORMAT_MONO10; + caps->screen_info = SCREEN_INFO_MONO_MSB_FIRST | SCREEN_INFO_EPD; +} + +static int gd7965_set_orientation(const struct device *dev, + const enum display_orientation + orientation) +{ + LOG_ERR("Unsupported"); + return -ENOTSUP; +} + +static int gd7965_set_pixel_format(const struct device *dev, + const enum display_pixel_format pf) +{ + if (pf == PIXEL_FORMAT_MONO10) { + return 0; + } + + LOG_ERR("not supported"); + return -ENOTSUP; +} + +static int gd7965_clear_and_write_buffer(struct device *dev, + u8_t pattern, bool update) +{ + struct display_buffer_descriptor desc = { + .buf_size = GD7965_NUMOF_PAGES, + .width = EPD_PANEL_WIDTH, + .height = 1, + .pitch = EPD_PANEL_WIDTH, + }; + u8_t *line; + + line = k_malloc(GD7965_NUMOF_PAGES); + if (line == NULL) { + return -ENOMEM; + } + + memset(line, pattern, GD7965_NUMOF_PAGES); + for (int i = 0; i < EPD_PANEL_HEIGHT; i++) { + gd7965_write(dev, 0, i, &desc, line); + } + + k_free(line); + + if (update == true) { + if (gd7965_update_display(dev)) { + return -EIO; + } + } + + return 0; +} + +static int gd7965_controller_init(struct device *dev) +{ + struct gd7965_data *driver = dev->driver_data; + u8_t tmp[GD7965_TRES_REG_LENGTH]; + + gpio_pin_write(driver->reset, GD7965_RESET_PIN, 0); + k_sleep(GD7965_RESET_DELAY); + gpio_pin_write(driver->reset, GD7965_RESET_PIN, 1); + k_sleep(GD7965_RESET_DELAY); + gd7965_busy_wait(driver); + + LOG_DBG("Initialize GD7965 controller"); + + if (gd7965_write_cmd(driver, GD7965_CMD_PWR, gd7965_pwr, + sizeof(gd7965_pwr))) { + return -EIO; + } + + if (gd7965_write_cmd(driver, GD7965_CMD_BTST, + gd7965_softstart, sizeof(gd7965_softstart))) { + return -EIO; + } + + /* Turn on: booster, controller, regulators, and sensor. */ + if (gd7965_write_cmd(driver, GD7965_CMD_PON, NULL, 0)) { + return -EIO; + } + + k_sleep(GD7965_PON_DELAY); + gd7965_busy_wait(driver); + + /* Pannel settings, KW mode */ + tmp[0] = GD7965_PSR_KW_R | + GD7965_PSR_UD | + GD7965_PSR_SHL | + GD7965_PSR_SHD | + GD7965_PSR_RST; + if (gd7965_write_cmd(driver, GD7965_CMD_PSR, tmp, 1)) { + return -EIO; + } + + /* Set panel resolution */ + sys_put_be16(EPD_PANEL_WIDTH, &tmp[GD7965_TRES_HRES_IDX]); + sys_put_be16(EPD_PANEL_HEIGHT, &tmp[GD7965_TRES_VRES_IDX]); + LOG_HEXDUMP_DBG(tmp, sizeof(tmp), "TRES"); + if (gd7965_write_cmd(driver, GD7965_CMD_TRES, + tmp, GD7965_TRES_REG_LENGTH)) { + return -EIO; + } + + bdd_polarity = GD7965_CDI_BDV1 | + GD7965_CDI_N2OCP | GD7965_CDI_DDX0; + tmp[GD7965_CDI_BDZ_DDX_IDX] = bdd_polarity; + tmp[GD7965_CDI_CDI_IDX] = DT_INST_0_GOODDISPLAY_GD7965_CDI; + LOG_HEXDUMP_DBG(tmp, GD7965_CDI_REG_LENGTH, "CDI"); + if (gd7965_write_cmd(driver, GD7965_CMD_CDI, tmp, + GD7965_CDI_REG_LENGTH)) { + return -EIO; + } + + tmp[0] = DT_INST_0_GOODDISPLAY_GD7965_TCON; + if (gd7965_write_cmd(driver, GD7965_CMD_TCON, tmp, 1)) { + return -EIO; + } + + /* Enable Auto Sequence */ + tmp[0] = GD7965_AUTO_PON_DRF_POF; + if (gd7965_write_cmd(driver, GD7965_CMD_AUTO, tmp, 1)) { + return -EIO; + } + + if (gd7965_clear_and_write_buffer(dev, 0xff, false)) { + return -1; + } + + return 0; +} + +static int gd7965_init(struct device *dev) +{ + struct gd7965_data *driver = dev->driver_data; + + LOG_DBG(""); + + driver->spi_dev = device_get_binding(GD7965_BUS_NAME); + if (driver->spi_dev == NULL) { + LOG_ERR("Could not get SPI device for GD7965"); + return -EIO; + } + + driver->spi_config.frequency = GD7965_SPI_FREQ; + driver->spi_config.operation = SPI_OP_MODE_MASTER | SPI_WORD_SET(8); + driver->spi_config.slave = DT_INST_0_GOODDISPLAY_GD7965_BASE_ADDRESS; + driver->spi_config.cs = NULL; + + driver->reset = device_get_binding(GD7965_RESET_CNTRL); + if (driver->reset == NULL) { + LOG_ERR("Could not get GPIO port for GD7965 reset"); + return -EIO; + } + + gpio_pin_configure(driver->reset, GD7965_RESET_PIN, + GPIO_DIR_OUT); + + driver->dc = device_get_binding(GD7965_DC_CNTRL); + if (driver->dc == NULL) { + LOG_ERR("Could not get GPIO port for GD7965 DC signal"); + return -EIO; + } + + gpio_pin_configure(driver->dc, GD7965_DC_PIN, + GPIO_DIR_OUT); + + driver->busy = device_get_binding(GD7965_BUSY_CNTRL); + if (driver->busy == NULL) { + LOG_ERR("Could not get GPIO port for GD7965 busy signal"); + return -EIO; + } + + gpio_pin_configure(driver->busy, GD7965_BUSY_PIN, + GPIO_DIR_IN); + +#if defined(GD7965_CS_CNTRL) + driver->cs_ctrl.gpio_dev = device_get_binding(GD7965_CS_CNTRL); + if (!driver->cs_ctrl.gpio_dev) { + LOG_ERR("Unable to get SPI GPIO CS device"); + return -EIO; + } + + driver->cs_ctrl.gpio_pin = GD7965_CS_PIN; + driver->cs_ctrl.delay = 0U; + driver->spi_config.cs = &driver->cs_ctrl; +#endif + + return gd7965_controller_init(dev); +} + +static struct gd7965_data gd7965_driver; + +static struct display_driver_api gd7965_driver_api = { + .blanking_on = gd7965_blanking_on, + .blanking_off = gd7965_blanking_off, + .write = gd7965_write, + .read = gd7965_read, + .get_framebuffer = gd7965_get_framebuffer, + .set_brightness = gd7965_set_brightness, + .set_contrast = gd7965_set_contrast, + .get_capabilities = gd7965_get_capabilities, + .set_pixel_format = gd7965_set_pixel_format, + .set_orientation = gd7965_set_orientation, +}; + + +DEVICE_AND_API_INIT(gd7965, DT_INST_0_GOODDISPLAY_GD7965_LABEL, gd7965_init, + &gd7965_driver, NULL, + POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY, + &gd7965_driver_api); diff --git a/drivers/display/gd7965_regs.h b/drivers/display/gd7965_regs.h new file mode 100644 index 00000000000..811e19b20fa --- /dev/null +++ b/drivers/display/gd7965_regs.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2020 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_DISPLAY_GD7965_REGS_H_ +#define ZEPHYR_DRIVERS_DISPLAY_GD7965_REGS_H_ + +#define GD7965_CMD_PSR 0x00 +#define GD7965_CMD_PWR 0x01 +#define GD7965_CMD_POF 0x02 +#define GD7965_CMD_PFS 0x03 +#define GD7965_CMD_PON 0x04 +#define GD7965_CMD_PMES 0x05 +#define GD7965_CMD_BTST 0x06 +#define GD7965_CMD_DSLP 0x07 +#define GD7965_CMD_DTM1 0x10 +#define GD7965_CMD_DSP 0x11 +#define GD7965_CMD_DRF 0x12 +#define GD7965_CMD_DTM2 0x13 +#define GD7965_CMD_DUSPI 0x15 +#define GD7965_CMD_AUTO 0x17 +#define GD7965_CMD_LUTOPT 0x2A +#define GD7965_CMD_KWOPT 0x2B +#define GD7965_CMD_PLL 0x30 +#define GD7965_CMD_TSC 0x40 +#define GD7965_CMD_TSE 0x41 +#define GD7965_CMD_TSW 0x42 +#define GD7965_CMD_TSR 0x43 +#define GD7965_CMD_PBC 0x44 +#define GD7965_CMD_CDI 0x50 +#define GD7965_CMD_LPD 0x51 +#define GD7965_CMD_EVS 0x52 +#define GD7965_CMD_TCON 0x60 +#define GD7965_CMD_TRES 0x61 +#define GD7965_CMD_GSST 0x65 +#define GD7965_CMD_REV 0x70 +#define GD7965_CMD_FLG 0x71 +#define GD7965_CMD_AMV 0x80 +#define GD7965_CMD_VV 0x81 +#define GD7965_CMD_VDCS 0x82 +#define GD7965_CMD_PTL 0x90 +#define GD7965_CMD_PTIN 0x91 +#define GD7965_CMD_PTOUT 0x92 +#define GD7965_CMD_PGM 0xA0 +#define GD7965_CMD_APG 0xA1 +#define GD7965_CMD_ROTP 0xA2 +#define GD7965_CMD_CCSET 0xE0 +#define GD7965_CMD_PWS 0xE3 +#define GD7965_CMD_LVSEL 0xE4 +#define GD7965_CMD_TSSET 0xE5 +#define GD7965_CMD_TSBDRY 0xE7 + +#define GD7965_PSR_REG BIT(5) +#define GD7965_PSR_KW_R BIT(4) +#define GD7965_PSR_UD BIT(3) +#define GD7965_PSR_SHL BIT(2) +#define GD7965_PSR_SHD BIT(1) +#define GD7965_PSR_RST BIT(0) + +#define GD7965_AUTO_PON_DRF_POF 0xA5 +#define GD7965_AUTO_PON_DRF_POF_DSLP 0xA7 + +#define GD7965_CDI_REG_LENGTH 2U +#define GD7965_CDI_BDZ_DDX_IDX 0 +#define GD7965_CDI_CDI_IDX 1 +#define GD7965_CDI_BDZ BIT(7) +#define GD7965_CDI_BDV1 BIT(5) +#define GD7965_CDI_BDV0 BIT(4) +#define GD7965_CDI_N2OCP BIT(3) +#define GD7965_CDI_DDX1 BIT(1) +#define GD7965_CDI_DDX0 BIT(0) + +#define GD7965_TRES_REG_LENGTH 4U +#define GD7965_TRES_HRES_IDX 0 +#define GD7965_TRES_VRES_IDX 2 + +#define GD7965_PTL_REG_LENGTH 9U +#define GD7965_PTL_HRST_IDX 0 +#define GD7965_PTL_HRED_IDX 2 +#define GD7965_PTL_VRST_IDX 4 +#define GD7965_PTL_VRED_IDX 6 +#define GD7965_PTL_PT_SCAN BIT(0) + +/* Time constants in ms */ +#define GD7965_RESET_DELAY 10U +#define GD7965_PON_DELAY 100U +#define GD7965_BUSY_DELAY 1U + +#endif /* ZEPHYR_DRIVERS_DISPLAY_GD7965_REGS_H_ */ diff --git a/dts/bindings/display/gooddisplay,gd7965.yaml b/dts/bindings/display/gooddisplay,gd7965.yaml new file mode 100644 index 00000000000..91f1b82a977 --- /dev/null +++ b/dts/bindings/display/gooddisplay,gd7965.yaml @@ -0,0 +1,51 @@ +# Copyright (c) 2020, Phytec Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +description: GD7965 EPD display controller + +compatible: "gooddisplay,gd7965" + +include: spi-device.yaml + +properties: + height: + type: int + required: true + description: Height in pixel of the panel driven by the controller + + width: + type: int + required: true + description: Width in pixel of the panel driven by the controller + + reset-gpios: + type: phandle-array + required: true + + dc-gpios: + type: phandle-array + required: true + + busy-gpios: + type: phandle-array + required: true + + pwr: + type: uint8-array + required: true + description: Power Setting (PWR) values + + softstart: + type: uint8-array + required: true + description: Booster Soft Start (BTST) values + + cdi: + type: int + required: true + description: VCOM and data interval value + + tcon: + type: int + required: true + description: TCON setting value