michaelh/zephyr
1
0
Fork 0
Code Releases Activity

arch: arm: core: aarch32: enable ARMv7-R/Cortex-R code for ARMv7-A/Cortex-A

Browse source 
Modify #ifdefs so that any code that is compiled if CONFIG_ARMV7_R is
set is also compiled if CONFIG_ARMV7_A is set.
Modify #ifdefs so that any code that is compiled if CONFIG_CPU_CORTEX_R
is set is also compiled if CONFIG_CPU_AARCH32_CORTEX_A is set.
Modify source dir inclusion in CMakeLists.txt accordingly.

Brief file descriptions have been updated to include Cortex-A whereever
only Cortex-M and Cortex-R were mentioned so far.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
This commit is contained in:
Immo Birnbaum 2021-07-15 10:49:19 +02:00 • committed by Carles Cufí
commit c6141c49c1
13 changed files with 42 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

4
include/arch/arm/aarch32/arch.h
View file

@ -37,7 +37,7 @@
#include <arch/arm/aarch32/cortex_m/cpu.h>
#include <arch/arm/aarch32/cortex_m/memory_map.h>
#include <arch/common/sys_io.h>
#elif defined(CONFIG_CPU_CORTEX_R)
#elif defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
#include <arch/arm/aarch32/cortex_a_r/cpu.h>
#include <arch/arm/aarch32/cortex_a_r/sys_io.h>
#include <arch/arm/aarch32/cortex_a_r/timer.h>
@ -71,7 +71,7 @@ extern "C" {
*/
#if defined(CONFIG_USERSPACE)
#define Z_THREAD_MIN_STACK_ALIGN CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
#elif defined(CONFIG_ARM_MMU)
#elif defined(CONFIG_ARM_AARCH32_MMU)
#define Z_THREAD_MIN_STACK_ALIGN CONFIG_ARM_MMU_REGION_MIN_ALIGN_AND_SIZE
#else
#define Z_THREAD_MIN_STACK_ALIGN ARCH_STACK_PTR_ALIGN

6
include/arch/arm/aarch32/asm_inline_gcc.h
View file

@ -22,7 +22,7 @@
#include <arch/arm/aarch32/exc.h>
#include <irq.h>
#if defined(CONFIG_CPU_CORTEX_R)
#if defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
#include <arch/arm/aarch32/cortex_a_r/cpu.h>
#endif
@ -61,7 +61,7 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
: "=r"(key), "=r"(tmp)
: "i"(_EXC_IRQ_DEFAULT_PRIO)
: "memory");
#elif defined(CONFIG_ARMV7_R)
#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
__asm__ volatile(
"mrs %0, cpsr;"
"and %0, #" TOSTR(I_BIT) ";"
@ -96,7 +96,7 @@ static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
"msr BASEPRI, %0;"
"isb;"
: : "r"(key) : "memory");
#elif defined(CONFIG_ARMV7_R)
#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
if (key != 0U) {
return;
}

2
include/arch/arm/aarch32/error.h
View file

@ -53,7 +53,7 @@ do { \
: [reason] "i" (reason_p), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \
: "memory"); \
} while (false)
#elif defined(CONFIG_ARMV7_R)
#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
/*
* In order to support using svc for an exception while running in an
* isr, stack $lr_svc before calling svc. While exiting the isr,