From c6141c49c15b3ba5784682d91f505ba6ec6b4dfc Mon Sep 17 00:00:00 2001 From: Immo Birnbaum Date: Thu, 15 Jul 2021 10:49:19 +0200 Subject: [PATCH] arch: arm: core: aarch32: enable ARMv7-R/Cortex-R code for ARMv7-A/Cortex-A Modify #ifdefs so that any code that is compiled if CONFIG_ARMV7_R is set is also compiled if CONFIG_ARMV7_A is set. Modify #ifdefs so that any code that is compiled if CONFIG_CPU_CORTEX_R is set is also compiled if CONFIG_CPU_AARCH32_CORTEX_A is set. Modify source dir inclusion in CMakeLists.txt accordingly. Brief file descriptions have been updated to include Cortex-A whereever only Cortex-M and Cortex-R were mentioned so far. Signed-off-by: Immo Birnbaum --- arch/arm/core/aarch32/CMakeLists.txt | 1 + arch/arm/core/aarch32/cpu_idle.S | 5 +++-- arch/arm/core/aarch32/irq_manage.c | 14 +++++++++----- arch/arm/core/aarch32/isr_wrapper.S | 14 +++++++------- arch/arm/core/aarch32/prep_c.c | 5 +++-- arch/arm/core/aarch32/swap.c | 2 +- arch/arm/core/aarch32/swap_helper.S | 10 +++++----- arch/arm/core/aarch32/thread.c | 9 +++++---- arch/arm/include/aarch32/cortex_a_r/stack.h | 2 +- arch/arm/include/kernel_arch_data.h | 2 +- include/arch/arm/aarch32/arch.h | 4 ++-- include/arch/arm/aarch32/asm_inline_gcc.h | 6 +++--- include/arch/arm/aarch32/error.h | 2 +- 13 files changed, 42 insertions(+), 34 deletions(-) diff --git a/arch/arm/core/aarch32/CMakeLists.txt b/arch/arm/core/aarch32/CMakeLists.txt index 2a51c5dcbbf..4cf0eaf9fb1 100644 --- a/arch/arm/core/aarch32/CMakeLists.txt +++ b/arch/arm/core/aarch32/CMakeLists.txt @@ -30,5 +30,6 @@ add_subdirectory_ifdef(CONFIG_ARM_MPU mpu) add_subdirectory_ifdef(CONFIG_ARM_AARCH32_MMU mmu) add_subdirectory_ifdef(CONFIG_CPU_CORTEX_R cortex_a_r) +add_subdirectory_ifdef(CONFIG_CPU_AARCH32_CORTEX_A cortex_a_r) zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld) diff --git a/arch/arm/core/aarch32/cpu_idle.S b/arch/arm/core/aarch32/cpu_idle.S index 603a0ecb4f1..837b8111ed5 100644 --- a/arch/arm/core/aarch32/cpu_idle.S +++ b/arch/arm/core/aarch32/cpu_idle.S @@ -6,7 +6,7 @@ /** * @file - * @brief ARM Cortex-M and Cortex-R power management + * @brief ARM Cortex-A, Cortex-M and Cortex-R power management * */ @@ -135,7 +135,8 @@ SECTION_FUNC(TEXT, arch_cpu_atomic_idle) /* r0: interrupt mask from caller */ #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \ - || defined(CONFIG_ARMV7_R) + || defined(CONFIG_ARMV7_R) \ + || defined(CONFIG_ARMV7_A) /* No BASEPRI, call wfe directly * (SEVONPEND is set in z_arm_cpu_idle_init()) */ diff --git a/arch/arm/core/aarch32/irq_manage.c b/arch/arm/core/aarch32/irq_manage.c index be0a3d03ed8..5b68e044bb9 100644 --- a/arch/arm/core/aarch32/irq_manage.c +++ b/arch/arm/core/aarch32/irq_manage.c @@ -6,7 +6,7 @@ /** * @file - * @brief ARM Cortex-M and Cortex-R interrupt management + * @brief ARM Cortex-A, Cortex-M and Cortex-R interrupt management * * * Interrupt management: enabling/disabling and dynamic ISR @@ -18,7 +18,8 @@ #include #if defined(CONFIG_CPU_CORTEX_M) #include -#elif defined(CONFIG_CPU_CORTEX_A) || defined(CONFIG_CPU_CORTEX_R) +#elif defined(CONFIG_CPU_AARCH32_CORTEX_A) \ + || defined(CONFIG_CPU_CORTEX_R) #include #endif #include @@ -92,7 +93,8 @@ void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) NVIC_SetPriority((IRQn_Type)irq, prio); } -#elif defined(CONFIG_CPU_CORTEX_A) || defined(CONFIG_CPU_CORTEX_R) +#elif defined(CONFIG_CPU_AARCH32_CORTEX_A) \ + || defined(CONFIG_CPU_CORTEX_R) /* * For Cortex-A and Cortex-R cores, the default interrupt controller is the ARM * Generic Interrupt Controller (GIC) and therefore the architecture interrupt @@ -162,7 +164,8 @@ void z_irq_spurious(const void *unused) void _arch_isr_direct_pm(void) { #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \ - || defined(CONFIG_ARMV7_R) + || defined(CONFIG_ARMV7_R) \ + || defined(CONFIG_ARMV7_A) unsigned int key; /* irq_lock() does what we wan for this CPU */ @@ -185,7 +188,8 @@ void _arch_isr_direct_pm(void) } #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \ - || defined(CONFIG_ARMV7_R) + || defined(CONFIG_ARMV7_R) \ + || defined(CONFIG_ARMV7_A) irq_unlock(key); #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) __asm__ volatile("cpsie i" : : : "memory"); diff --git a/arch/arm/core/aarch32/isr_wrapper.S b/arch/arm/core/aarch32/isr_wrapper.S index 0f60ade2ca3..b21be826e4c 100644 --- a/arch/arm/core/aarch32/isr_wrapper.S +++ b/arch/arm/core/aarch32/isr_wrapper.S @@ -7,7 +7,7 @@ /** * @file - * @brief ARM Cortex-M and Cortex-R wrapper for ISRs with parameter + * @brief ARM Cortex-A, Cortex-M and Cortex-R wrapper for ISRs with parameter * * Wrapper installed in vector table for handling dynamic interrupts that accept * a parameter. @@ -48,7 +48,7 @@ SECTION_FUNC(TEXT, _isr_wrapper) #if defined(CONFIG_CPU_CORTEX_M) push {r0,lr} /* r0, lr are now the first items on the stack */ -#elif defined(CONFIG_CPU_CORTEX_R) +#elif defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) #if defined(CONFIG_USERSPACE) /* See comment below about svc stack usage */ @@ -164,7 +164,7 @@ _idle_state_cleared: /* clear kernel idle state */ strne r1, [r2, #_kernel_offset_to_idle] blne z_pm_save_idle_exit -#elif defined(CONFIG_ARMV7_R) +#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) beq _idle_state_cleared movs r1, #0 /* clear kernel idle state */ @@ -191,7 +191,7 @@ _idle_state_cleared: sub r0, r0, #16 /* get IRQ number */ lsl r0, r0, #3 /* table is 8-byte wide */ #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ -#elif defined(CONFIG_CPU_CORTEX_R) +#elif defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) /* Get active IRQ number from the interrupt controller */ #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) bl arm_gic_get_active @@ -233,7 +233,7 @@ _idle_state_cleared: ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */ blx r3 /* call ISR */ -#if defined(CONFIG_CPU_CORTEX_R) +#if defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) spurious_continue: /* Signal end-of-interrupt */ pop {r0, r1} @@ -242,7 +242,7 @@ spurious_continue: #else bl z_soc_irq_eoi #endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */ -#endif /* CONFIG_CPU_CORTEX_R */ +#endif /* CONFIG_CPU_CORTEX_R || CONFIG_CPU_AARCH32_CORTEX_A */ #ifdef CONFIG_TRACING_ISR bl sys_trace_isr_exit @@ -253,7 +253,7 @@ spurious_continue: mov lr, r3 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) pop {r0, lr} -#elif defined(CONFIG_ARMV7_R) +#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) /* * r0 and lr_irq were saved on the process stack since a swap could * happen. exc_exit will handle getting those values back diff --git a/arch/arm/core/aarch32/prep_c.c b/arch/arm/core/aarch32/prep_c.c index 94e97457e4b..88cd0eb0764 100644 --- a/arch/arm/core/aarch32/prep_c.c +++ b/arch/arm/core/aarch32/prep_c.c @@ -20,7 +20,7 @@ #include #include -#if defined(CONFIG_ARMV7_R) +#if defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) #include #endif @@ -166,6 +166,7 @@ static inline void z_arm_floating_point_init(void) #endif /* CONFIG_CPU_HAS_FPU */ extern FUNC_NORETURN void z_cstart(void); + /** * * @brief Prepare to and run C code @@ -182,7 +183,7 @@ void z_arm_prep_c(void) #endif z_bss_zero(); z_data_copy(); -#if defined(CONFIG_ARMV7_R) && defined(CONFIG_INIT_STACKS) +#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS)) z_arm_init_stacks(); #endif z_arm_interrupt_init(); diff --git a/arch/arm/core/aarch32/swap.c b/arch/arm/core/aarch32/swap.c index f2fb9fe24ae..f54238a3805 100644 --- a/arch/arm/core/aarch32/swap.c +++ b/arch/arm/core/aarch32/swap.c @@ -42,7 +42,7 @@ int arch_swap(unsigned int key) /* clear mask or enable all irqs to take a pendsv */ irq_unlock(0); -#elif defined(CONFIG_CPU_CORTEX_R) +#elif defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) z_arm_cortex_r_svc(); irq_unlock(key); #endif diff --git a/arch/arm/core/aarch32/swap_helper.S b/arch/arm/core/aarch32/swap_helper.S index 67bf266c6fc..6a0f884051f 100644 --- a/arch/arm/core/aarch32/swap_helper.S +++ b/arch/arm/core/aarch32/swap_helper.S @@ -11,7 +11,7 @@ * @brief Thread context switching for ARM Cortex-M and Cortex-R * * This module implements the routines necessary for thread context switching - * on ARM Cortex-M and Cortex-R CPUs. + * on ARM Cortex-A, Cortex-M and Cortex-R CPUs. */ #include @@ -120,7 +120,7 @@ out_fp_endif: * regardless of whether the thread has an active FP context. */ #endif /* CONFIG_FPU_SHARING */ -#elif defined(CONFIG_ARMV7_R) +#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) /* Store rest of process context */ cps #MODE_SYS stm r0, {r4-r11, sp} @@ -136,7 +136,7 @@ out_fp_endif: movs.n r0, #_EXC_IRQ_DEFAULT_PRIO msr BASEPRI_MAX, r0 isb /* Make the effect of disabling interrupts be realized immediately */ -#elif defined(CONFIG_ARMV7_R) +#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) /* * Interrupts are still disabled from arch_swap so empty clause * here to avoid the preprocessor error below @@ -344,7 +344,7 @@ in_fp_endif: /* load callee-saved + psp from thread */ add r0, r2, #_thread_offset_to_callee_saved ldmia r0, {v1-v8, ip} -#elif defined(CONFIG_ARMV7_R) +#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) _thread_irq_disabled: /* load _kernel into r1 and current k_thread into r2 */ ldr r1, =_kernel @@ -603,7 +603,7 @@ valid_syscall_id: bx lr #endif /* CONFIG_USERSPACE */ -#elif defined(CONFIG_ARMV7_R) +#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) /** * diff --git a/arch/arm/core/aarch32/thread.c b/arch/arm/core/aarch32/thread.c index 8c48389a4b2..1184f94d04d 100644 --- a/arch/arm/core/aarch32/thread.c +++ b/arch/arm/core/aarch32/thread.c @@ -6,10 +6,10 @@ /** * @file - * @brief New thread creation for ARM Cortex-M and Cortex-R + * @brief New thread creation for ARM Cortex-A, Cortex-M and Cortex-R * - * Core thread related primitives for the ARM Cortex-M and Cortex-R - * processor architecture. + * Core thread related primitives for the ARM Cortex-A, Cortex-M and + * Cortex-R processor architecture. */ #include @@ -562,7 +562,8 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr, "movs r1, #0\n\t" #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \ - || defined(CONFIG_ARMV7_R) + || defined(CONFIG_ARMV7_R) \ + || defined(CONFIG_ARMV7_A) "cpsie i\n\t" /* __enable_irq() */ #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) "cpsie if\n\t" /* __enable_irq(); __enable_fault_irq() */ diff --git a/arch/arm/include/aarch32/cortex_a_r/stack.h b/arch/arm/include/aarch32/cortex_a_r/stack.h index 0ef544d6f55..cab5ec03227 100644 --- a/arch/arm/include/aarch32/cortex_a_r/stack.h +++ b/arch/arm/include/aarch32/cortex_a_r/stack.h @@ -30,7 +30,7 @@ extern void z_arm_init_stacks(void); * * @brief Setup interrupt stack * - * On Cortex-R, the interrupt stack is set up by reset.S + * On Cortex-A and Cortex-R, the interrupt stack is set up by reset.S * * @return N/A */ diff --git a/arch/arm/include/kernel_arch_data.h b/arch/arm/include/kernel_arch_data.h index af22d2d6976..a6f1b734969 100644 --- a/arch/arm/include/kernel_arch_data.h +++ b/arch/arm/include/kernel_arch_data.h @@ -27,7 +27,7 @@ #if defined(CONFIG_CPU_CORTEX_M) #include #include -#elif defined(CONFIG_CPU_CORTEX_R) +#elif defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) #include #include #endif diff --git a/include/arch/arm/aarch32/arch.h b/include/arch/arm/aarch32/arch.h index 0c203f80dae..6155a0f2e83 100644 --- a/include/arch/arm/aarch32/arch.h +++ b/include/arch/arm/aarch32/arch.h @@ -37,7 +37,7 @@ #include #include #include -#elif defined(CONFIG_CPU_CORTEX_R) +#elif defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) #include #include #include @@ -71,7 +71,7 @@ extern "C" { */ #if defined(CONFIG_USERSPACE) #define Z_THREAD_MIN_STACK_ALIGN CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE -#elif defined(CONFIG_ARM_MMU) +#elif defined(CONFIG_ARM_AARCH32_MMU) #define Z_THREAD_MIN_STACK_ALIGN CONFIG_ARM_MMU_REGION_MIN_ALIGN_AND_SIZE #else #define Z_THREAD_MIN_STACK_ALIGN ARCH_STACK_PTR_ALIGN diff --git a/include/arch/arm/aarch32/asm_inline_gcc.h b/include/arch/arm/aarch32/asm_inline_gcc.h index 7d492224a66..104fc964663 100644 --- a/include/arch/arm/aarch32/asm_inline_gcc.h +++ b/include/arch/arm/aarch32/asm_inline_gcc.h @@ -22,7 +22,7 @@ #include #include -#if defined(CONFIG_CPU_CORTEX_R) +#if defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) #include #endif @@ -61,7 +61,7 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void) : "=r"(key), "=r"(tmp) : "i"(_EXC_IRQ_DEFAULT_PRIO) : "memory"); -#elif defined(CONFIG_ARMV7_R) +#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) __asm__ volatile( "mrs %0, cpsr;" "and %0, #" TOSTR(I_BIT) ";" @@ -96,7 +96,7 @@ static ALWAYS_INLINE void arch_irq_unlock(unsigned int key) "msr BASEPRI, %0;" "isb;" : : "r"(key) : "memory"); -#elif defined(CONFIG_ARMV7_R) +#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) if (key != 0U) { return; } diff --git a/include/arch/arm/aarch32/error.h b/include/arch/arm/aarch32/error.h index d58f0b27d30..975da29b48c 100644 --- a/include/arch/arm/aarch32/error.h +++ b/include/arch/arm/aarch32/error.h @@ -53,7 +53,7 @@ do { \ : [reason] "i" (reason_p), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \ : "memory"); \ } while (false) -#elif defined(CONFIG_ARMV7_R) +#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) /* * In order to support using svc for an exception while running in an * isr, stack $lr_svc before calling svc. While exiting the isr,