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cavs: remove unused mcuboot support

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CONFIG_BOOTLOADER_MCUBOOT is never used in cAVS builds, remove
code, supposedly supporting it.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit is contained in:
Guennadi Liakhovetski 2021-01-04 16:40:50 +01:00 • committed by Anas Nashif
commit c5a763f607
4 changed files with 0 additions and 20 deletions
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5
soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
View file

@ -17,13 +17,8 @@
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#ifdef CONFIG_BOOTLOADER_MCUBOOT
#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#else
#define SRAM_BASE (L2_SRAM_BASE) #define SRAM_BASE (L2_SRAM_BASE)
#define SRAM_SIZE (L2_SRAM_SIZE) #define SRAM_SIZE (L2_SRAM_SIZE)
#endif
/* The reset vector address in SRAM and its size */ /* The reset vector address in SRAM and its size */
#define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE #define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE

5
soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
View file

@ -14,13 +14,8 @@
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#ifdef CONFIG_BOOTLOADER_MCUBOOT
#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#else
#define SRAM_BASE (L2_SRAM_BASE) #define SRAM_BASE (L2_SRAM_BASE)
#define SRAM_SIZE (L2_SRAM_SIZE) #define SRAM_SIZE (L2_SRAM_SIZE)
#endif
/* The reset vector address in SRAM and its size */ /* The reset vector address in SRAM and its size */
#define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE #define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE

5
soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
View file

@ -14,13 +14,8 @@
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#ifdef CONFIG_BOOTLOADER_MCUBOOT
#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#else
#define SRAM_BASE (L2_SRAM_BASE) #define SRAM_BASE (L2_SRAM_BASE)
#define SRAM_SIZE (L2_SRAM_SIZE) #define SRAM_SIZE (L2_SRAM_SIZE)
#endif
/* The reset vector address in SRAM and its size */ /* The reset vector address in SRAM and its size */
#define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE #define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE

5
soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
View file

@ -14,13 +14,8 @@
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#ifdef CONFIG_BOOTLOADER_MCUBOOT
#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#else
#define SRAM_BASE (L2_SRAM_BASE) #define SRAM_BASE (L2_SRAM_BASE)
#define SRAM_SIZE (L2_SRAM_SIZE) #define SRAM_SIZE (L2_SRAM_SIZE)
#endif
/* The reset vector address in SRAM and its size */ /* The reset vector address in SRAM and its size */
#define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE #define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE