From c5a763f60781590b756f9ab7b5ec9cae314185c1 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Mon, 4 Jan 2021 16:40:50 +0100 Subject: [PATCH] cavs: remove unused mcuboot support CONFIG_BOOTLOADER_MCUBOOT is never used in cAVS builds, remove code, supposedly supporting it. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h | 5 ----- soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h | 5 ----- soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h | 5 ----- soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h | 5 ----- 4 files changed, 20 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h index d852fb80ad5..2bfb93f66a4 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h @@ -17,13 +17,8 @@ #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) -#ifdef CONFIG_BOOTLOADER_MCUBOOT -#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#else #define SRAM_BASE (L2_SRAM_BASE) #define SRAM_SIZE (L2_SRAM_SIZE) -#endif /* The reset vector address in SRAM and its size */ #define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h index 612ae6198f1..8e10613d11f 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h @@ -14,13 +14,8 @@ #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) -#ifdef CONFIG_BOOTLOADER_MCUBOOT -#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#else #define SRAM_BASE (L2_SRAM_BASE) #define SRAM_SIZE (L2_SRAM_SIZE) -#endif /* The reset vector address in SRAM and its size */ #define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h index 7a35852a6b3..58e44e4f3b2 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h @@ -14,13 +14,8 @@ #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) -#ifdef CONFIG_BOOTLOADER_MCUBOOT -#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#else #define SRAM_BASE (L2_SRAM_BASE) #define SRAM_SIZE (L2_SRAM_SIZE) -#endif /* The reset vector address in SRAM and its size */ #define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index 42b9ca81d53..8b5a59b25e2 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -14,13 +14,8 @@ #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) -#ifdef CONFIG_BOOTLOADER_MCUBOOT -#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#else #define SRAM_BASE (L2_SRAM_BASE) #define SRAM_SIZE (L2_SRAM_SIZE) -#endif /* The reset vector address in SRAM and its size */ #define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE