arch: arm64: Fix the cache coherence issue

Accessing mem before mmu or mpu init will cause a cache coherence issue.
To avoid such a problem, move the safe exception stack init function
after the mmu or mpu is initiated.

Also change the data section attribute from INNER_SHAREABLE to
OUTER_SHAREABLE. Otherwise there will be a cache coherence issue during
the memory regions switch. Because we are using background region to do
the regions switch, and the default background region is
OUTER_SHAREABLE, if we use INNER_SHAREABLE as the foreground region,
then we have to flush all cache regions to make sure the cached values
are right. However, flushing all regions is too heavy, so we set
OUTER_SHAREABLE to fix this issue.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>

arch/arm64/core/smp.c

@@ -141,12 +141,13 @@ void z_arm64_secondary_start(void)
 
 	/* Initialize tpidrro_el0 with our struct _cpu instance address */
 	write_tpidrro_el0((uintptr_t)&_kernel.cpus[cpu_num]);
+
+	z_arm64_mm_init(false);
+
 #ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK
 	z_arm64_safe_exception_stack_init();
 #endif
 
-	z_arm64_mm_init(false);
-
 #ifdef CONFIG_SMP
 	arm_gic_secondary_init();
 

include/zephyr/arch/arm64/cortex_r/arm_mpu.h

@@ -143,7 +143,7 @@
 #define REGION_RAM_ATTR							\
 	{								\
 		/* AP, XN, SH */					\
-		.rbar = NOT_EXEC | P_RW_U_NA_Msk | INNER_SHAREABLE_Msk, \
+		.rbar = NOT_EXEC | P_RW_U_NA_Msk | OUTER_SHAREABLE_Msk, \
 		/* Cache-ability */					\
 		.mair_idx = MPU_MAIR_INDEX_SRAM,			\
 	}