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soc_beetle: Add initial PM configuration

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This patch adds the boot time Power Management configuration for Beetle
on Zephyr. In particular it defines the states of the peripherals during
sleep and deep sleep and the allowed wakeup sources.

Jira: ZEP-1300
Change-Id: Iad9c0f851771ea60d94bbe5420b7b3ee0743b77e
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This commit is contained in:
Vincenzo Frascino 2016-11-01 12:15:44 +00:00 • committed by Kumar Gala
commit c4e5126519
6 changed files with 282 additions and 43 deletions
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2
arch/arm/soc/arm/beetle/Makefile
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@ -16,4 +16,4 @@
# limitations under the License.
#
obj-y += soc.o
obj-y += soc.o power.o

138
arch/arm/soc/arm/beetle/power.c Normal file
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@ -0,0 +1,138 @@
/*
* Copyright (c) 2016 Linaro Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <device.h>
#include <init.h>
#include <power.h>
#include <soc.h>
#include <soc_power.h>
#include <arch/cpu.h>
#ifdef CONFIG_GPIO_CMSDK_AHB_PORT0
#define CLK_BIT_GPIO0 _BEETLE_GPIO0
#else
#define CLK_BIT_GPIO0 0
#endif
#ifdef CONFIG_GPIO_CMSDK_AHB_PORT1
#define CLK_BIT_GPIO1 _BEETLE_GPIO1
#else
#define CLK_BIT_GPIO1 0
#endif
#define AHB_CLK_BITS (CLK_BIT_GPIO0 | CLK_BIT_GPIO1)
#if defined(CONFIG_COUNTER_TMR_CMSDK_APB_0)
#define CLK_BIT_TIMER0 _BEETLE_TIMER0
#else
#define CLK_BIT_TIMER0 0
#endif
#if defined(CONFIG_COUNTER_TMR_CMSDK_APB_1)
#define CLK_BIT_TIMER1 _BEETLE_TIMER1
#else
#define CLK_BIT_TIMER1 0
#endif
#ifdef CONFIG_RUNTIME_NMI
#define CLK_BIT_WDOG _BEETLE_WDOG
#else
#define CLK_BIT_WDOG 0
#endif
#ifdef CONFIG_UART_CMSDK_APB_PORT0
#define CLK_BIT_UART0 _BEETLE_UART0
#else
#define CLK_BIT_UART0 0
#endif
#ifdef CONFIG_UART_CMSDK_APB_PORT1
#define CLK_BIT_UART1 _BEETLE_UART1
#else
#define CLK_BIT_UART1 0
#endif
#define APB_CLK_BITS (CLK_BIT_TIMER0 | CLK_BIT_TIMER1 \
| CLK_BIT_WDOG | CLK_BIT_UART0 | CLK_BIT_UART1)
/**
* @brief Setup various clock on SoC in active state.
*
* Configures the clock in active state.
*/
static ALWAYS_INLINE void clock_active_init(void)
{
/* Enable AHB and APB clocks */
/* Configure AHB Peripheral Clock in active state */
__BEETLE_SYSCON->ahbclkcfg0set = AHB_CLK_BITS;
/* Configure APB Peripheral Clock in active state */
__BEETLE_SYSCON->apbclkcfg0set = APB_CLK_BITS;
}
/**
* @brief Configures the clock that remain active during sleep state.
*
* Configures the clock that remain active during sleep state.
*/
static ALWAYS_INLINE void clock_sleep_init(void)
{
/* Configure APB Peripheral Clock in sleep state */
__BEETLE_SYSCON->apbclkcfg1set = APB_CLK_BITS;
}
/**
* @brief Configures the clock that remain active during deepsleep state.
*
* Configures the clock that remain active during deepsleep state.
*/
static ALWAYS_INLINE void clock_deepsleep_init(void)
{
/* Configure APB Peripheral Clock in deep sleep state */
__BEETLE_SYSCON->apbclkcfg2set = APB_CLK_BITS;
}
/**
* @brief Setup initial wakeup sources on SoC.
*
* Setup the SoC wakeup sources.
*
*/
static ALWAYS_INLINE void wakeup_src_init(void)
{
/* Configure Wakeup Sources */
__BEETLE_SYSCON->pwrdncfg1set = APB_CLK_BITS;
}
/**
* @brief Setup various clocks and wakeup sources in the SoC.
*
* Configures the clocks and wakeup sources in the SoC.
*/
void soc_power_init(void)
{
/* Setup active state clocks */
clock_active_init();
/* Setup sleep active clocks */
clock_sleep_init();
/* Setup deepsleep active clocks */
clock_deepsleep_init();
/* Setup initial wakeup sources */
wakeup_src_init();
}

52
arch/arm/soc/arm/beetle/soc.c
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@ -22,47 +22,12 @@
* for the ARM LTD Beetle SoC.
*/
#include <nanokernel.h>
#include <device.h>
#include <init.h>
#include <soc.h>
#include <nanokernel.h>
#include <device.h>
#include <init.h>
#include <soc.h>
#include <arch/cpu.h>
/**
* @brief Setup various clock on SoC.
*
* Setup the SoC clocks.
*
* Assumption:
* MAINCLK = 24Mhz
*/
static ALWAYS_INLINE void clock_init(void)
{
/* Enable AHB and APB clocks */
/* GPIO */
__BEETLE_SYSCON->ahbclkcfg0set = _BEETLE_GPIO0
| _BEETLE_GPIO1
| _BEETLE_GPIO2
| _BEETLE_GPIO3;
/*
* Activate clock for: I2C1, SPI1, SPIO, QUADSPI, WDOG,
* I2C0, UART0, UART1, TIMER0, TIMER1, DUAL TIMER, TRNG
*/
__BEETLE_SYSCON->apbclkcfg0set = _BEETLE_TIMER0
| _BEETLE_TIMER1
| _BEETLE_DUALTIMER0
| _BEETLE_UART0
| _BEETLE_UART1
| _BEETLE_I2C0
| _BEETLE_WDOG
| _BEETLE_QSPI
| _BEETLE_SPI0
| _BEETLE_SPI1
| _BEETLE_I2C1
| _BEETLE_TRNG;
}
#include <arch/cpu.h>
/**
* @brief Perform basic hardware initialization at boot.
@ -70,6 +35,9 @@ static ALWAYS_INLINE void clock_init(void)
* This needs to be run from the very beginning.
* So the init priority has to be 0 (zero).
*
* Assumption:
* MAINCLK = 24Mhz
*
* @return 0
*/
static int arm_beetle_init(struct device *arg)
@ -80,8 +48,8 @@ static int arm_beetle_init(struct device *arg)
key = irq_lock();
/* Setup master clock */
clock_init();
/* Setup various clocks and wakeup sources */
soc_power_init();
/* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise

24
arch/arm/soc/arm/beetle/soc.h
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@ -69,8 +69,20 @@
#define _BEETLE_SYSCON_BASE (_BEETLE_AHB_BASE + 0xF000)
/* Beetle SoC APB peripherals */
#define _BEETLE_TIMER0_BASE (_BEETLE_APB_BASE + 0x0000)
#define _BEETLE_TIMER1_BASE (_BEETLE_APB_BASE + 0x1000)
#define _BEETLE_DTIMER_BASE (_BEETLE_APB_BASE + 0x2000)
#define _BEETLE_FCACHE_BASE (_BEETLE_APB_BASE + 0x3000)
#define _BEETLE_UART0_BASE (_BEETLE_APB_BASE + 0x4000)
#define _BEETLE_UART1_BASE (_BEETLE_APB_BASE + 0x5000)
#define _BEETLE_RTC_BASE (_BEETLE_APB_BASE + 0x6000)
#define _BEETLE_I2C0_BASE (_BEETLE_APB_BASE + 0x7000)
#define _BEETLE_WDOG_BASE (_BEETLE_APB_BASE + 0x8000)
#define _BEETLE_QSPI_BASE (_BEETLE_APB_BASE + 0xB000)
#define _BEETLE_SPI0_BASE (_BEETLE_APB_BASE + 0xC000)
#define _BEETLE_SPI1_BASE (_BEETLE_APB_BASE + 0xD000)
#define _BEETLE_I2C1_BASE (_BEETLE_APB_BASE + 0xE000)
#define _BEETLE_TRNG_BASE (_BEETLE_APB_BASE + 0xF000)
#ifndef _ASMLANGUAGE
@ -78,7 +90,9 @@
#include <misc/util.h>
#include "soc_pins.h"
#include "soc_power.h"
#include "soc_registers.h"
#include "soc_pll.h"
/* System Control Register (SYSCON) */
#define __BEETLE_SYSCON ((volatile struct syscon *)_BEETLE_SYSCON_BASE)
@ -89,10 +103,20 @@
#define CMSDK_AHB_GPIO2 _BEETLE_GPIO2_BASE
#define CMSDK_AHB_GPIO3 _BEETLE_GPIO3_BASE
/* CMSDK APB Timers */
#define CMSDK_APB_TIMER0 _BEETLE_TIMER0_BASE
#define CMSDK_APB_TIMER1 _BEETLE_TIMER1_BASE
/* CMSDK APB Dual Timer */
#define CMSDK_APB_DTIMER _BEETLE_DTIMER_BASE
/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */
#define CMSDK_APB_UART0 _BEETLE_UART0_BASE
#define CMSDK_APB_UART1 _BEETLE_UART1_BASE
/* CMSDK APB Watchdog */
#define CMSDK_APB_WDOG _BEETLE_WDOG_BASE
#endif /* !_ASMLANGUAGE */
#endif /* _ARM_BEETLE_SOC_H_ */

74
arch/arm/soc/arm/beetle/soc_pll.h Normal file
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@ -0,0 +1,74 @@
/*
* Copyright (c) 2016 Linaro Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file SoC configuration macros for the ARM LTD Beetle SoC PLL.
*
*/
#ifndef _ARM_BEETLE_SOC_PLL_H_
#define _ARM_BEETLE_SOC_PLL_H_
/*
* This header provides the defines to configure the Beetle PLL.
*
* BEETLE PLL main register is the PLLCTRL in the System Control
*
* The PLLCTRL relevant bits are:
* - PLL_OUTPUTDIV [9:8]
* - PLL_INPUTDIV [20:16]
* - PLL_FEEDDIV [30:24]
*
* The formula to calculate the output frequency of the PLL is:
* Fout = Fin * PLL_FEEDDIV / (PLL_INPUTDIV * PLL_OUTPUTDIV)
* The Fin = 24Mhz on Beetle
*
* PLL_OUTPUTDIV | 0 1 2 3
* -----------------------
* | 1 2 4 8
*
* PLL_INPUTDIV = R[20:16] + 1
*
* PLL_FEEDDIV = 2*(R[30:24] + 1)
*
* BEETLE PLL has a non bypassable divider by 2 in output
*
* BEETLE PLL derived clock is prescaled [1-16]
*/
/* BEETLE PLL Masks */
#define PLL_MAINCLK_ENABLE_Msk 0x1
#define PLL_MAINCLK_DISABLE_Msk 0x1
#define PLL_MAINCLK_PRESCALER_Msk 0xF0
/* BEETLE PLL Configuration */
#define BEETLE_PLL_CONFIGURATION 0x17000200
/* BEETLE PLL Supported Frequencies */
/* BEETLE_PLL_48Mhz */
#define BEETLE_PLL_FREQUENCY_48MHZ 48000000
#define BEETLE_PLL_PRESCALER_48MHZ 0x21
/* BEETLE_PLL_36Mhz */
#define BEETLE_PLL_FREQUENCY_36MHZ 36000000
#define BEETLE_PLL_PRESCALER_36MHZ 0x31
/* BEETLE_PLL_24Mhz */
#define BEETLE_PLL_FREQUENCY_24MHZ 24000000
#define BEETLE_PLL_PRESCALER_24MHZ 0x51
/* BEETLE_PLL_12Mhz */
#define BEETLE_PLL_FREQUENCY_12MHZ 12000000
#define BEETLE_PLL_PRESCALER_12MHZ 0xB1
#endif /* _ARM_BEETLE_SOC_PLL_H_ */

35
arch/arm/soc/arm/beetle/soc_power.h Normal file
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@ -0,0 +1,35 @@
/*
* Copyright (c) 2016 Linaro Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _SOC_POWER_H_
#define _SOC_POWER_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Setup various clocks and wakeup sources in the SoC.
*
* Configures the clocks and wakeup sources in the SoC.
*/
void soc_power_init(void);
#ifdef __cplusplus
}
#endif
#endif /* _SOC_POWER_H_ */