xtensa: ADSP: Intel: fix booting on APL with XCC
When built with XCC for Apollolake, Zephyr fails to boot with the default multi-core option enabled. Invalidate cache before reading the firmware image to fix that. Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
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1 changed files with 4 additions and 0 deletions
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@ -68,6 +68,7 @@ static inline void bmemcpy(void *dest, void *src, size_t bytes)
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uint32_t *s = src;
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uint32_t *s = src;
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int i;
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int i;
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z_xtensa_cache_inv(src, bytes);
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for (i = 0; i < (bytes >> 2); i++)
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for (i = 0; i < (bytes >> 2); i++)
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d[i] = s[i];
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d[i] = s[i];
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@ -167,10 +168,13 @@ static void parse_manifest(void)
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struct sof_man_module *mod;
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struct sof_man_module *mod;
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int i;
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int i;
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z_xtensa_cache_inv(hdr, sizeof(*hdr));
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/* copy module to SRAM - skip bootloader module */
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/* copy module to SRAM - skip bootloader module */
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for (i = MAN_SKIP_ENTRIES; i < hdr->num_module_entries; i++) {
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for (i = MAN_SKIP_ENTRIES; i < hdr->num_module_entries; i++) {
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mod = (void *)((uintptr_t)desc + SOF_MAN_MODULE_OFFSET(i));
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mod = (void *)((uintptr_t)desc + SOF_MAN_MODULE_OFFSET(i));
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z_xtensa_cache_inv(mod, sizeof(*mod));
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parse_module(hdr, mod);
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parse_module(hdr, mod);
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}
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}
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}
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}
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