From c2400a47ab556359b542151d051c9dcaa73eb044 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 7 Oct 2021 10:48:35 +0200 Subject: [PATCH] xtensa: ADSP: Intel: fix booting on APL with XCC When built with XCC for Apollolake, Zephyr fails to boot with the default multi-core option enabled. Invalidate cache before reading the firmware image to fix that. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/common/bootloader/boot_loader.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c index f6e63c70bd3..e7a219f7574 100644 --- a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c +++ b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c @@ -68,6 +68,7 @@ static inline void bmemcpy(void *dest, void *src, size_t bytes) uint32_t *s = src; int i; + z_xtensa_cache_inv(src, bytes); for (i = 0; i < (bytes >> 2); i++) d[i] = s[i]; @@ -167,10 +168,13 @@ static void parse_manifest(void) struct sof_man_module *mod; int i; + z_xtensa_cache_inv(hdr, sizeof(*hdr)); + /* copy module to SRAM - skip bootloader module */ for (i = MAN_SKIP_ENTRIES; i < hdr->num_module_entries; i++) { mod = (void *)((uintptr_t)desc + SOF_MAN_MODULE_OFFSET(i)); + z_xtensa_cache_inv(mod, sizeof(*mod)); parse_module(hdr, mod); } }