From c1ae6e5b4e8e084a639efd1c1fa560296eb4ad8d Mon Sep 17 00:00:00 2001 From: Adrien MARTIN Date: Thu, 18 Jan 2024 08:48:47 +0100 Subject: [PATCH] soc: stm32g0: add fdcan2 The STM32G0 soc has 2 CAN controllers. The 2nd on was not working with zephyr yet as both controllers shares the same IRQ. Recently, the shared irq system was integrated on now, both can controllers can work on this chip. Shared interrupts must be enabled only if both can controllers are enabled. Signed-off-by: Adrien MARTIN --- dts/arm/st/g0/stm32g0b1.dtsi | 13 +++++++++++++ .../st_stm32/stm32g0/Kconfig.defconfig.stm32g0b1xx | 7 +++++++ 2 files changed, 20 insertions(+) diff --git a/dts/arm/st/g0/stm32g0b1.dtsi b/dts/arm/st/g0/stm32g0b1.dtsi index 28b55fc70de..f6a8ae129e0 100644 --- a/dts/arm/st/g0/stm32g0b1.dtsi +++ b/dts/arm/st/g0/stm32g0b1.dtsi @@ -43,6 +43,19 @@ status = "disabled"; }; + fdcan2: can@40006800 { + compatible = "st,stm32-fdcan"; + reg = <0x40006800 0x400>, <0x4000b750 0x350>; + reg-names = "m_can", "message_ram"; + interrupts = <21 0>, <22 0>; + interrupt-names = "int0", "int1"; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>; + bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; + sample-point = <875>; + sample-point-data = <875>; + status = "disabled"; + }; + usart5: serial@40005000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40005000 0x400>; diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b1xx b/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b1xx index 86c47b158e9..767cea2556c 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b1xx +++ b/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b1xx @@ -11,4 +11,11 @@ config SOC config NUM_IRQS default 31 +if CAN_STM32_FDCAN + +config SHARED_INTERRUPTS + default y if $(dt_nodelabel_enabled,fdcan1) && $(dt_nodelabel_enabled,fdcan2) + +endif # CAN_STM32_FDCAN + endif # SOC_STM32G0B1XX