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soc: cavs_v25: Clean up platform config to reflect recent work

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Use the built-in IDC handling and not IPM (which is limited to two
CPUs).  Declare two cpus for now, Zephyr tests are having problems
with more at the moment (that isn't a CI configuration, so we may have
work to do).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2021-08-12 09:05:01 -07:00 • committed by Anas Nashif
commit bfe3f8806b
2 changed files with 5 additions and 17 deletions
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21
soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series
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@ -15,6 +15,10 @@ config SOC
string string
default "intel_cavs_25" default "intel_cavs_25"
# Hardware has four cores, limited to two pending test fixes
config MP_NUM_CPUS
default 2
config SMP config SMP
default y default y
@ -66,21 +70,4 @@ config LOG_BACKEND_ADSP
endif # LOG endif # LOG
if SMP
# FIXME: these DSPs can have more cores, but Zephyr only supports up to 2 cores on them
config MP_NUM_CPUS
default 2
config IPM
default y
config IPM_CAVS_IDC
default y if IPM
config SCHED_IPI_SUPPORTED
default y if IPM_CAVS_IDC
endif # SMP
endif # SOC_SERIES_INTEL_CAVS_V25 endif # SOC_SERIES_INTEL_CAVS_V25

1
soc/xtensa/intel_adsp/cavs_v25/Kconfig.series
View file

@ -10,5 +10,6 @@ config SOC_SERIES_INTEL_CAVS_V25
select XTENSA_USE_CORE_CRT1 select XTENSA_USE_CORE_CRT1
select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
select ARCH_HAS_COHERENCE select ARCH_HAS_COHERENCE
select SCHED_IPI_SUPPORTED
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Intel CAVS v2.5 Intel CAVS v2.5