xtensa: Add exception/interrupt vectors in asm2 mode
This adds vectors for all interrupt levels defined by core-isa.h. Modify the entry code a little bit to select correct linker sections (levels 1, 6 and 7 get special names for... no particularly good reason) and to constructed the interrupted PS value correctly (no EPS1 register for exceptions since they had to have interrupted level 0 code and thus differ only in the EXCM bit). Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross
Anas Nashif
parent
7de010b5e5
commit
bf2139331c
4 changed files with 291 additions and 20 deletions
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@ -4,6 +4,7 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa-asm2-s.h>
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#include <offsets.h>
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/*
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* xtensa_save_high_regs
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@ -207,3 +208,60 @@ xtensa_switch:
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j _restore_context
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_switch_restore_pc:
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retw
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#ifdef CONFIG_XTENSA_ASM2
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/* Define our entry handler to load the struct kernel_t from the
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* MISC0 special register, and to find the nest and irq_stack values
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* at the precomputed offsets.
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*/
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.align 4
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_handle_excint:
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EXCINT_HANDLER MISC0, ___kernel_t_nested_OFFSET, ___kernel_t_irq_stack_OFFSET
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/* Define the actual vectors for the hardware-defined levels with
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* DEF_EXCINT. These load a C handler address and jump to our handler
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* above.
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*/
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DEF_EXCINT 1, _handle_excint, xtensa_excint1_c
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#if XCHAL_NMILEVEL >= 2
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DEF_EXCINT 2, _handle_excint, xtensa_int2_c
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#endif
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#if XCHAL_NMILEVEL >= 3
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DEF_EXCINT 3, _handle_excint, xtensa_int3_c
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#endif
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#if XCHAL_NMILEVEL >= 4
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DEF_EXCINT 4, _handle_excint, xtensa_int4_c
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#endif
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#if XCHAL_NMILEVEL >= 5
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DEF_EXCINT 5, _handle_excint, xtensa_int5_c
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#endif
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#if XCHAL_NMILEVEL >= 6
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DEF_EXCINT 6, _handle_excint, xtensa_int6_c
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#endif
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#if XCHAL_NMILEVEL >= 7
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DEF_EXCINT 7, _handle_excint, xtensa_int7_c
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#endif
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/* In theory you can have levels up to 15, but known hardware only uses 7. */
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#if XCHAL_NMILEVEL > 7
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#error More interrupts than expected.
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#endif
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/* We don't actually use "kernel mode" currently. Populate the vector
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* out of simple caution in case app code clears the UM bit by mistake.
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*/
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.pushsection .KernelExceptionVector.text, "ax"
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.global _KernelExceptionVector
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_KernelExceptionVector:
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j _Level1Vector
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.popsection
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#endif /* CONFIG_XTENSA_ASM2 */
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@ -3,10 +3,13 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <misc/printk.h>
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#include <string.h>
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#include <xtensa-asm2.h>
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#include <kernel.h>
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#include <ksched.h>
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#include <kernel_structs.h>
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#include <_soc_inthandlers.h>
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void *xtensa_init_stack(int *stack_top,
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void (*entry)(void *, void *, void *),
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@ -49,16 +52,169 @@ void *xtensa_init_stack(int *stack_top,
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return &bsa[-9];
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}
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/* This is a kernel hook, just a wrapper around other APIs. Build
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* only if we're using asm2 as the core OS interface and not just as
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* utilities/testables.
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*/
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#ifdef CONFIG_XTENSA_ASM2
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void _new_thread(struct k_thread *thread, k_thread_stack_t *stack, size_t sz,
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k_thread_entry_t entry, void *p1, void *p2, void *p3,
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int prio, unsigned int opts)
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{
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char *base = K_THREAD_STACK_BUFFER(stack);
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char *top = base + sz;
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__ASSERT((((size_t)top) & 3) == 0, "Misaligned stack");
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_new_thread_init(thread, base, sz, prio, opts);
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thread->switch_handle = xtensa_init_stack(top, entry, p1, p2, p3);
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thread->switch_handle = xtensa_init_stack((void *)top, entry,
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p1, p2, p3);
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}
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#endif
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#ifdef CONFIG_XTENSA_ASM2
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void _irq_spurious(void *arg)
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{
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int irqs, ie;
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ARG_UNUSED(arg);
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__asm__ volatile("rsr.interrupt %0" : "=r"(irqs));
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__asm__ volatile("rsr.intenable %0" : "=r"(ie));
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printk(" ** Spurious INTERRUPT(s) %p, INTENABLE = %p\n",
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(void *)irqs, (void *)ie);
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_NanoFatalErrorHandler(_NANO_ERR_RESERVED_IRQ, &_default_esf);
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}
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#endif
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static void dump_stack(int *stack)
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{
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int *bsa = *(int **)stack;
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printk(" ** A0 %p SP %p A2 %p A3 %p\n",
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(void *)bsa[BSA_A0_OFF/4], ((char *)bsa) + BASE_SAVE_AREA_SIZE,
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(void *)bsa[BSA_A2_OFF/4], (void *)bsa[BSA_A3_OFF/4]);
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if (bsa - stack > 4) {
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printk(" ** A4 %p A5 %p A6 %p A7 %p\n",
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(void *)bsa[-4], (void *)bsa[-3],
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(void *)bsa[-2], (void *)bsa[-1]);
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}
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if (bsa - stack > 8) {
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printk(" ** A8 %p A9 %p A10 %p A11 %p\n",
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(void *)bsa[-8], (void *)bsa[-7],
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(void *)bsa[-6], (void *)bsa[-5]);
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}
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if (bsa - stack > 12) {
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printk(" ** A12 %p A13 %p A14 %p A15 %p\n",
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(void *)bsa[-12], (void *)bsa[-11],
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(void *)bsa[-10], (void *)bsa[-9]);
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}
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#if XCHAL_HAVE_LOOPS
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printk(" ** LBEG %p LEND %p LCOUNT %p\n",
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(void *)bsa[BSA_LBEG_OFF/4],
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(void *)bsa[BSA_LEND_OFF/4],
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(void *)bsa[BSA_LCOUNT_OFF/4]);
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#endif
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printk(" ** SAR %p\n", (void *)bsa[BSA_SAR_OFF/4]);
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}
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#if CONFIG_XTENSA_ASM2
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static inline void *restore_stack(void *interrupted_stack)
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{
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int key = irq_lock();
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_kernel.current->switch_handle = interrupted_stack;
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_kernel.current = _get_next_ready_thread();
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void *ret = _kernel.current->switch_handle;
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irq_unlock(key);
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return ret;
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}
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#endif
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/* The wrapper code lives here instead of in the python script that
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* generates _xtensa_handle_one_int*(). Seems cleaner, still kind of
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* ugly.
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*/
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#define DEF_INT_C_HANDLER(l) \
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void *xtensa_int##l##_c(void *interrupted_stack) \
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{ \
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int irqs, m; \
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__asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \
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\
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while ((m = _xtensa_handle_one_int##l(irqs))) { \
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irqs ^= m; \
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__asm__ volatile("wsr.intclear %0" : : "r"(m)); \
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} \
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return restore_stack(interrupted_stack); \
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}
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DEF_INT_C_HANDLER(2)
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DEF_INT_C_HANDLER(3)
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DEF_INT_C_HANDLER(4)
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DEF_INT_C_HANDLER(5)
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DEF_INT_C_HANDLER(6)
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DEF_INT_C_HANDLER(7)
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static inline DEF_INT_C_HANDLER(1)
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/* C handler for level 1 exceptions/interrupts. Hooked from the
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* DEF_EXCINT 1 vector declaration in assembly code. This one looks
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* different because exceptions and interrupts land at the same
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* vector; other interrupt levels have their own vectors.
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*/
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void *xtensa_excint1_c(int *interrupted_stack)
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{
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int cause, vaddr, *bsa = *(int **)interrupted_stack;
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__asm__ volatile("rsr.exccause %0" : "=r"(cause));
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if (cause == EXCCAUSE_LEVEL1_INTERRUPT) {
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return xtensa_int1_c(interrupted_stack);
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} else if (cause == EXCCAUSE_SYSCALL) {
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/* Just report it to the console for now */
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printk(" ** SYSCALL PS %p PC %p\n",
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(void *)bsa[BSA_PS_OFF/4], (void *)bsa[BSA_PC_OFF/4]);
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dump_stack(interrupted_stack);
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/* Xtensa exceptions don't automatically advance PC,
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* have to skip the SYSCALL instruction manually or
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* else it will just loop forever
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*/
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bsa[BSA_PC_OFF/4] += 3;
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} else {
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__asm__ volatile("rsr.excvaddr %0" : "=r"(vaddr));
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/* Wouldn't hurt to translate EXCCAUSE to a string for
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* the user...
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*/
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printk(" ** FATAL EXCEPTION\n");
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printk(" ** EXCCAUSE %d PS %p PC %p VADDR %p\n",
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cause, (void *)bsa[BSA_PS_OFF/4],
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(void *)bsa[BSA_PC_OFF/4], (void *)vaddr);
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dump_stack(interrupted_stack);
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/* FIXME: legacy xtensa port reported "HW" exception
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* for all unhandled exceptions, which seems incorrect
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* as these are software errors. Should clean this
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* up.
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*/
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_NanoFatalErrorHandler(_NANO_ERR_HW_EXCEPTION, &_default_esf);
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}
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return restore_stack(interrupted_stack);
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}
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@ -26,6 +26,8 @@ extern void ReservedInterruptHandler(unsigned int intNo);
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/* Defined in xtensa_context.S */
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extern void _xt_coproc_init(void);
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extern K_THREAD_STACK_DEFINE(_interrupt_stack, CONFIG_ISR_STACK_SIZE);
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/**
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*
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* @brief Performs architecture-specific initialization
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@ -39,7 +41,23 @@ extern void _xt_coproc_init(void);
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static ALWAYS_INLINE void kernel_arch_init(void)
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{
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_kernel.nested = 0;
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#if XCHAL_CP_NUM > 0
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#if CONFIG_XTENSA_ASM2
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_kernel.irq_stack = (K_THREAD_STACK_BUFFER(_interrupt_stack) +
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CONFIG_ISR_STACK_SIZE);
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/* The asm2 scheme keeps the kernel pointer in MISC0 for easy
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* access. That saves 4 bytes of immediate value to store the
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* address when compared to the legacy scheme. But in SMP
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* this record is a per-CPU thing and having it stored in a SR
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* already is a big win.
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*/
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void *cpuptr = &_kernel;
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__asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(cpuptr));
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#endif
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#if !defined(CONFIG_XTENSA_ASM2) && XCHAL_CP_NUM > 0
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/* Initialize co-processor management for threads.
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* Leave CPENABLE alone.
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*/
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@ -231,12 +231,34 @@ _xstack_returned_\@:
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l32i a2, a1, 0
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l32i a2, a2, BSA_SCRATCH_OFF
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/* There's a gotcha with level 1 handlers: the INTLEVEL field
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* gets left at zero and not set like high priority interrupts
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* do. That works fine for exceptions, but for L1 interrupts,
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* when we unmask EXCM below, the CPU will just fire the
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* interrupt again and get stuck in a loop blasting save
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* frames down the stack to the bottom of memory. It would be
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* good to put this code into the L1 handler only, but there's
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* not enough room in the vector without some work there to
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* squash it some. Next choice would be to make this a macro
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* argument and expand two versions of this handler. An
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* optimization FIXME, I guess.
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*/
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rsr.PS a0
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movi a3, PS_INTLEVEL_MASK
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and a0, a0, a3
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bnez a0, _not_l1
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rsr.PS a0
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movi a3, PS_INTLEVEL(1)
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or a0, a0, a3
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wsr.PS a0
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_not_l1:
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/* Unmask EXCM bit so C code can spill/fill in window
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* exceptions. Note interrupts are already fully masked by
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* INTLEVEL, so this is safe.
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*/
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rsr.PS a0
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movi a3, ~16
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movi a3, ~(PS_EXCM_MASK)
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and a0, a0, a3
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wsr.PS a0
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rsync
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@ -297,17 +319,21 @@ _restore_\@:
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* entry code (defined via EXCINT_HANDLER) and a C handler for this
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* particular level.
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*
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* FIXME: needs special handling for exceptions (level 1): it's "EPC"
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* and not "EPC1" (though IIRC the assembler makes this work).
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* And there is no EPS: instead PS is simply the interrupted PS
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* with EXCM flipped from 0 to 1.
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*
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* FIXME: needs better locking. The hardware will NOT mask out "high
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* priority" exceptions on arrival here, so we have to do it ourselves
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* with RSIL.
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* Note that the linker sections for some levels get special names for
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* no particularly good reason. Only level 1 has any code generation
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* difference, because it is the legacy exception level that predates
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* the EPS/EPC registers.
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*/
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.macro DEF_EXCINT LVL, ENTRY_SYM, C_HANDLER_SYM
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.if \LVL == 1
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.pushsection .UserExceptionVector.text, "ax"
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.elseif \LVL == XCHAL_DEBUGLEVEL
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.pushsection .DebugExceptionVector.text, "ax"
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.elseif \LVL == XCHAL_NMILEVEL
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.pushsection .NMIExceptionVector.text, "ax"
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.else
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.pushsection .Level\LVL\()InterruptVector.text, "ax"
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.endif
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.global _Level\LVL\()Vector
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_Level\LVL\()Vector:
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addi a1, a1, -BASE_SAVE_AREA_SIZE
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@ -315,8 +341,21 @@ _Level\LVL\()Vector:
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s32i a2, a1, BSA_A2_OFF
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s32i a3, a1, BSA_A3_OFF
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/* Level "1" is the exception handler, which uses a different
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* calling convention. No special register holds the
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* interrupted PS, instead we just assume that the CPU has
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* turned on the EXCM bit and set INTLEVEL.
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*/
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.if \LVL == 1
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rsr.PS a0
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movi a2, ~(PS_EXCM_MASK | PS_INTLEVEL_MASK)
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and a0, a0, a2
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s32i a0, a1, BSA_PS_OFF
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.else
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rsr.EPS\LVL a0
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s32i a0, a1, BSA_PS_OFF
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.endif
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rsr.EPC\LVL a0
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s32i a0, a1, BSA_PC_OFF
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