xtensa: Interrupt generator script and output for qemu & esp32
This python script reads the core-isa.h interrupt definitions (via running a template file through the toolchain preprocessor to generate an input file) and emits a fully populated, optimized C handling code that binary searches only the declared interrupts at a given level and correctly detects spurious interrupts (and/or incorrect core-isa.h definitions). The generated code, alas, turns out not to be any faster than simply searching the interrupt mask with CLZ (er, NSAU in xtensese), though it could be faster in theory if the compiler made different choices, see comments. But I like this for the robustness of the fully populated search trees and the checking of level vs. mask. This simply commits the script output into the source tree, including some checking code to force a build error if the toolchain changes the headers incompatibly. It would be better long term to have these headers be generated at build time, but that requires more cmake fu than I have. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross
Anas Nashif
parent
bba98a9c38
commit
7de010b5e5
4 changed files with 812 additions and 0 deletions
129
arch/xtensa/core/xtensa_intgen.py
Executable file
129
arch/xtensa/core/xtensa_intgen.py
Executable file
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#!/usr/bin/env python3
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import re
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import fileinput
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# Pass an Xtensa core-isa.h file on stdin or the command line, emits a
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# C file on output containing optimized interrupt dispatch routines.
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# FIXME: looking at the assembly generated by the ESP-32 toolchain,
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# this isn't as optimal as I'd hoped. the individual cases are tested
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# using a L32R + BNONE (i.e. a full mask test) instead of a BBSI, and
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# the handlers are being invoked with CALL8 instead of CALL4,
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# inexplicably wasting four words of stack. Maybe this should be
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# emitting assembly instead. Wouldn't be much more complicated and
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# would share all the same structure.
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# My manual count of instructions says that a linear search becomes
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# faster on average when there are three or fewer bits to test. Would
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# be four, if the compiler would generate BBSI instructions.
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MAX_TESTS = 3
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ints_by_lvl = {}
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# print() wrapper that automatically handles indentation levels
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cindent = 0
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def cprint(s):
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global cindent
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if s.find("}") >= 0:
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cindent -= 1
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for xx in range(cindent):
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s = "\t" + s
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print(s)
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if s.find("{") >= 0:
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cindent += 1
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def emit_int_handler(ints):
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if len(ints) <= MAX_TESTS:
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for i in ints:
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# FIXME: a little work could allow us to extract the
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# handler pointer and argument as literals, saving a few
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# instructions and avoiding the need to link in
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# _sw_isr_table entirely.
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cprint("if (mask & (1 << " + str(i) + ")) {")
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cprint("struct _isr_table_entry *e = &_sw_isr_table[" + str(i) + "];")
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print("");
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cprint("e->isr(e->arg);")
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cprint("return 1 << " + str(i) + ";")
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cprint("}")
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else:
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half = int(len(ints)/2)
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m = 0
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for i in ints[0:half]:
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m |= 1 << i
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cprint("if (mask & " + ("0x%x" % (m)) + ") {")
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emit_int_handler(ints[0:half])
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cprint("} else {")
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emit_int_handler(ints[half:])
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cprint("}")
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########################################################################
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# Annoyingly need to join lines and remove #-marked annotations. Some
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# versions of the preprocessor (ahem, esp32 SDK) like to include
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# newlines in the output where the original expressions are expanded
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# from 100% single line macros. Slurp it into a single string and
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# parse via whitespace.
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blob = ""
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for l in fileinput.input():
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l = l if l.find("#") < 0 else l[0:l.find("#")]
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blob += l.rstrip() + " "
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for match in re.finditer(r'__xtensa_int_level_magic__\s+(\d+)\s+(\d+)', blob):
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irq = int(match.group(1))
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lvl = int(match.group(2))
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if not lvl in ints_by_lvl:
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ints_by_lvl[lvl] = []
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ints_by_lvl[lvl].append(irq)
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cprint("/*")
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cprint(" * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.")
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cprint(" *")
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cprint(" * Functions here are designed to produce efficient code to")
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cprint(" * search an Xtensa bitmask of interrupts, inspecting only those bits")
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cprint(" * declared to be associated with a given interrupt level. Each")
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cprint(" * dispatcher will handle exactly one flagged interrupt, in numerical")
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cprint(" * order (low bits first) and will return a mask of that bit that can")
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cprint(" * then be cleared by the calling code. Unrecognized bits for the")
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cprint(" * level will invoke an error handler.")
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cprint(" */")
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cprint("")
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# Re-include the core-isa header and be sure our definitions match, for sanity
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cprint("#include <xtensa/config/core-isa.h>")
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cprint("#include <sw_isr_table.h>")
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cprint("")
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for l in ints_by_lvl:
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for i in ints_by_lvl[l]:
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v = "XCHAL_INT" + str(i) + "_LEVEL"
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cprint("#if !defined(" + v + ") || " + str(v) + " != " + str(l))
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cprint("#error core-isa.h interrupt level does not match dispatcher!")
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cprint("#endif")
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cprint("")
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# Populate empty levels just for sanity. The second-to-last interrupt
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# level (usually "debug") typically doesn't have any associated
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# vectors, but we don't have any way to know that a-prioi.
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max = 0
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for lvl in ints_by_lvl:
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if lvl > max:
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max = lvl
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for lvl in range(0, max+1):
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if not lvl in ints_by_lvl:
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ints_by_lvl[lvl] = []
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# Emit the handlers
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for lvl in ints_by_lvl:
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cprint("static inline int _xtensa_handle_one_int" + str(lvl) + "(unsigned int mask)")
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cprint("{")
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ints_by_lvl[lvl].sort()
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emit_int_handler(ints_by_lvl[lvl])
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cprint("return 0;")
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cprint("}")
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cprint("")
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43
arch/xtensa/core/xtensa_intgen.tmpl
Normal file
43
arch/xtensa/core/xtensa_intgen.tmpl
Normal file
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#include <xtensa/config/core-isa.h>
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/*
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* Not a C source code file.
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*
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* Intended to be preprocessed only, to produce output for
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* interpretation by the xtensa-int-handlers.py script. Literally all
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* this does is emit records for which interrupts are at which level,
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* available per-hardware by an SDK-provided core-isa.h file.
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*/
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__xtensa_int_level_magic__ 0 XCHAL_INT0_LEVEL
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__xtensa_int_level_magic__ 1 XCHAL_INT1_LEVEL
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__xtensa_int_level_magic__ 2 XCHAL_INT2_LEVEL
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__xtensa_int_level_magic__ 3 XCHAL_INT3_LEVEL
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__xtensa_int_level_magic__ 4 XCHAL_INT4_LEVEL
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__xtensa_int_level_magic__ 5 XCHAL_INT5_LEVEL
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__xtensa_int_level_magic__ 6 XCHAL_INT6_LEVEL
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__xtensa_int_level_magic__ 7 XCHAL_INT7_LEVEL
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__xtensa_int_level_magic__ 8 XCHAL_INT8_LEVEL
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__xtensa_int_level_magic__ 9 XCHAL_INT9_LEVEL
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__xtensa_int_level_magic__ 10 XCHAL_INT10_LEVEL
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__xtensa_int_level_magic__ 11 XCHAL_INT11_LEVEL
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__xtensa_int_level_magic__ 12 XCHAL_INT12_LEVEL
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__xtensa_int_level_magic__ 13 XCHAL_INT13_LEVEL
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__xtensa_int_level_magic__ 14 XCHAL_INT14_LEVEL
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__xtensa_int_level_magic__ 15 XCHAL_INT15_LEVEL
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__xtensa_int_level_magic__ 16 XCHAL_INT16_LEVEL
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__xtensa_int_level_magic__ 17 XCHAL_INT17_LEVEL
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__xtensa_int_level_magic__ 18 XCHAL_INT18_LEVEL
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__xtensa_int_level_magic__ 19 XCHAL_INT19_LEVEL
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__xtensa_int_level_magic__ 20 XCHAL_INT20_LEVEL
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__xtensa_int_level_magic__ 21 XCHAL_INT21_LEVEL
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__xtensa_int_level_magic__ 22 XCHAL_INT22_LEVEL
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__xtensa_int_level_magic__ 23 XCHAL_INT23_LEVEL
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__xtensa_int_level_magic__ 24 XCHAL_INT24_LEVEL
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__xtensa_int_level_magic__ 25 XCHAL_INT25_LEVEL
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__xtensa_int_level_magic__ 26 XCHAL_INT26_LEVEL
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__xtensa_int_level_magic__ 27 XCHAL_INT27_LEVEL
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__xtensa_int_level_magic__ 28 XCHAL_INT28_LEVEL
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__xtensa_int_level_magic__ 29 XCHAL_INT29_LEVEL
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__xtensa_int_level_magic__ 30 XCHAL_INT30_LEVEL
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__xtensa_int_level_magic__ 31 XCHAL_INT31_LEVEL
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368
arch/xtensa/soc/esp32/include/_soc_inthandlers.h
Normal file
368
arch/xtensa/soc/esp32/include/_soc_inthandlers.h
Normal file
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/*
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* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
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*
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* Functions here are designed to produce efficient code to
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* search an Xtensa bitmask of interrupts, inspecting only those bits
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* declared to be associated with a given interrupt level. Each
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* dispatcher will handle exactly one flagged interrupt, in numerical
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* order (low bits first) and will return a mask of that bit that can
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* then be cleared by the calling code. Unrecognized bits for the
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* level will invoke an error handler.
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*/
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#include <xtensa/config/core-isa.h>
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#include <sw_isr_table.h>
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#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 4
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 4
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 4
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 4
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 5
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 5
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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static inline int _xtensa_handle_one_int0(unsigned int mask)
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{
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return 0;
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}
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static inline int _xtensa_handle_one_int1(unsigned int mask)
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{
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if (mask & 0x7f) {
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if (mask & 0x7) {
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if (mask & (1 << 0)) {
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struct _isr_table_entry *e = &_sw_isr_table[0];
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e->isr(e->arg);
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return 1 << 0;
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}
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if (mask & (1 << 1)) {
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struct _isr_table_entry *e = &_sw_isr_table[1];
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e->isr(e->arg);
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return 1 << 1;
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}
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if (mask & (1 << 2)) {
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struct _isr_table_entry *e = &_sw_isr_table[2];
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e->isr(e->arg);
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return 1 << 2;
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}
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} else {
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if (mask & 0x18) {
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if (mask & (1 << 3)) {
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struct _isr_table_entry *e = &_sw_isr_table[3];
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e->isr(e->arg);
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return 1 << 3;
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}
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if (mask & (1 << 4)) {
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struct _isr_table_entry *e = &_sw_isr_table[4];
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e->isr(e->arg);
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return 1 << 4;
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}
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} else {
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if (mask & (1 << 5)) {
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struct _isr_table_entry *e = &_sw_isr_table[5];
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e->isr(e->arg);
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return 1 << 5;
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}
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if (mask & (1 << 6)) {
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struct _isr_table_entry *e = &_sw_isr_table[6];
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e->isr(e->arg);
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return 1 << 6;
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}
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}
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}
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} else {
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if (mask & 0x780) {
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if (mask & 0x180) {
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if (mask & (1 << 7)) {
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struct _isr_table_entry *e = &_sw_isr_table[7];
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e->isr(e->arg);
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return 1 << 7;
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}
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if (mask & (1 << 8)) {
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struct _isr_table_entry *e = &_sw_isr_table[8];
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e->isr(e->arg);
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return 1 << 8;
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}
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} else {
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if (mask & (1 << 9)) {
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struct _isr_table_entry *e = &_sw_isr_table[9];
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e->isr(e->arg);
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return 1 << 9;
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}
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if (mask & (1 << 10)) {
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struct _isr_table_entry *e = &_sw_isr_table[10];
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e->isr(e->arg);
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return 1 << 10;
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}
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}
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} else {
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if (mask & 0x3000) {
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if (mask & (1 << 12)) {
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struct _isr_table_entry *e = &_sw_isr_table[12];
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e->isr(e->arg);
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return 1 << 12;
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}
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if (mask & (1 << 13)) {
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struct _isr_table_entry *e = &_sw_isr_table[13];
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e->isr(e->arg);
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return 1 << 13;
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}
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} else {
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if (mask & (1 << 17)) {
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struct _isr_table_entry *e = &_sw_isr_table[17];
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e->isr(e->arg);
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return 1 << 17;
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}
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if (mask & (1 << 18)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[18];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 18;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int2(unsigned int mask)
|
||||
{
|
||||
if (mask & (1 << 19)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[19];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 19;
|
||||
}
|
||||
if (mask & (1 << 20)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[20];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 20;
|
||||
}
|
||||
if (mask & (1 << 21)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[21];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 21;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int3(unsigned int mask)
|
||||
{
|
||||
if (mask & 0x408800) {
|
||||
if (mask & (1 << 11)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[11];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 11;
|
||||
}
|
||||
if (mask & (1 << 15)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[15];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 15;
|
||||
}
|
||||
if (mask & (1 << 22)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[22];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 22;
|
||||
}
|
||||
} else {
|
||||
if (mask & (1 << 23)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[23];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 23;
|
||||
}
|
||||
if (mask & (1 << 27)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[27];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 27;
|
||||
}
|
||||
if (mask & (1 << 29)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[29];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 29;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int4(unsigned int mask)
|
||||
{
|
||||
if (mask & 0x3000000) {
|
||||
if (mask & (1 << 24)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[24];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 24;
|
||||
}
|
||||
if (mask & (1 << 25)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[25];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 25;
|
||||
}
|
||||
} else {
|
||||
if (mask & (1 << 28)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[28];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 28;
|
||||
}
|
||||
if (mask & (1 << 30)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[30];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 30;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int5(unsigned int mask)
|
||||
{
|
||||
if (mask & (1 << 16)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[16];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 16;
|
||||
}
|
||||
if (mask & (1 << 26)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[26];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 26;
|
||||
}
|
||||
if (mask & (1 << 31)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[31];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 31;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int6(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int7(unsigned int mask)
|
||||
{
|
||||
if (mask & (1 << 14)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[14];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 14;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
272
arch/xtensa/soc/sample_controller/include/_soc_inthandlers.h
Normal file
272
arch/xtensa/soc/sample_controller/include/_soc_inthandlers.h
Normal file
|
|
@ -0,0 +1,272 @@
|
|||
/*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*
|
||||
* Functions here are designed to produce efficient code to
|
||||
* search an Xtensa bitmask of interrupts, inspecting only those bits
|
||||
* declared to be associated with a given interrupt level. Each
|
||||
* dispatcher will handle exactly one flagged interrupt, in numerical
|
||||
* order (low bits first) and will return a mask of that bit that can
|
||||
* then be cleared by the calling code. Unrecognized bits for the
|
||||
* level will invoke an error handler.
|
||||
*/
|
||||
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <sw_isr_table.h>
|
||||
|
||||
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 4
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 5
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
|
||||
static inline int _xtensa_handle_one_int0(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int1(unsigned int mask)
|
||||
{
|
||||
if (mask & 0x7f) {
|
||||
if (mask & 0x7) {
|
||||
if (mask & (1 << 0)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[0];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 0;
|
||||
}
|
||||
if (mask & (1 << 1)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[1];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 1;
|
||||
}
|
||||
if (mask & (1 << 2)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[2];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 2;
|
||||
}
|
||||
} else {
|
||||
if (mask & 0x18) {
|
||||
if (mask & (1 << 3)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[3];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 3;
|
||||
}
|
||||
if (mask & (1 << 4)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[4];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 4;
|
||||
}
|
||||
} else {
|
||||
if (mask & (1 << 5)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[5];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 5;
|
||||
}
|
||||
if (mask & (1 << 6)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[6];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 6;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (mask & 0x18080) {
|
||||
if (mask & (1 << 7)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[7];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 7;
|
||||
}
|
||||
if (mask & (1 << 15)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[15];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 15;
|
||||
}
|
||||
if (mask & (1 << 16)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[16];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 16;
|
||||
}
|
||||
} else {
|
||||
if (mask & 0x60000) {
|
||||
if (mask & (1 << 17)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[17];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 17;
|
||||
}
|
||||
if (mask & (1 << 18)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[18];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 18;
|
||||
}
|
||||
} else {
|
||||
if (mask & (1 << 19)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[19];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 19;
|
||||
}
|
||||
if (mask & (1 << 20)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[20];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 20;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int2(unsigned int mask)
|
||||
{
|
||||
if (mask & (1 << 8)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[8];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 8;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int3(unsigned int mask)
|
||||
{
|
||||
if (mask & 0x600) {
|
||||
if (mask & (1 << 9)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[9];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 9;
|
||||
}
|
||||
if (mask & (1 << 10)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[10];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 10;
|
||||
}
|
||||
} else {
|
||||
if (mask & (1 << 11)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[11];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 11;
|
||||
}
|
||||
if (mask & (1 << 21)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[21];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 21;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int4(unsigned int mask)
|
||||
{
|
||||
if (mask & (1 << 12)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[12];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 12;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int5(unsigned int mask)
|
||||
{
|
||||
if (mask & (1 << 13)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[13];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 13;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int6(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int7(unsigned int mask)
|
||||
{
|
||||
if (mask & (1 << 14)) {
|
||||
struct _isr_table_entry *e = &_sw_isr_table[14];
|
||||
|
||||
e->isr(e->arg);
|
||||
return 1 << 14;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue