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driver: uart_stm32: add support for stm32f2 series

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clear RXNE flag in fifo_read, remove TEACK and REACK
check when uart_stm32_init because stm32f2 doesn't
has those flags.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
This commit is contained in:
qianfan Zhao 2018-05-16 12:36:25 +08:00 • committed by Kumar Gala
commit bdeece01b8
5 changed files with 134 additions and 1 deletions
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36
arch/arm/soc/st_stm32/stm32f2/dts.fixup
View file

@ -2,4 +2,40 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS ST_STM32_USART_40011000_BASE_ADDRESS
#define CONFIG_UART_STM32_USART_1_BAUD_RATE ST_STM32_USART_40011000_CURRENT_SPEED
#define CONFIG_UART_STM32_USART_1_IRQ_PRI ST_STM32_USART_40011000_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_USART_1_NAME ST_STM32_USART_40011000_LABEL
#define USART_1_IRQ ST_STM32_USART_40011000_IRQ_0
#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS
#define CONFIG_UART_STM32_USART_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED
#define CONFIG_UART_STM32_USART_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_USART_2_NAME ST_STM32_USART_40004400_LABEL
#define USART_2_IRQ ST_STM32_USART_40004400_IRQ_0
#define CONFIG_UART_STM32_USART_3_BASE_ADDRESS ST_STM32_USART_40004800_BASE_ADDRESS
#define CONFIG_UART_STM32_USART_3_BAUD_RATE ST_STM32_USART_40004800_CURRENT_SPEED
#define CONFIG_UART_STM32_USART_3_IRQ_PRI ST_STM32_USART_40004800_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_USART_3_NAME ST_STM32_USART_40004800_LABEL
#define USART_3_IRQ ST_STM32_USART_40004800_IRQ_0
#define CONFIG_UART_STM32_USART_6_NAME ST_STM32_USART_40011400_LABEL
#define CONFIG_UART_STM32_USART_6_BASE_ADDRESS ST_STM32_USART_40011400_BASE_ADDRESS
#define CONFIG_UART_STM32_USART_6_BAUD_RATE ST_STM32_USART_40011400_CURRENT_SPEED
#define CONFIG_UART_STM32_USART_6_IRQ_PRI ST_STM32_USART_40011400_IRQ_0_PRIORITY
#define USART_6_IRQ ST_STM32_USART_40011400_IRQ_0
#define CONFIG_UART_STM32_UART_4_NAME ST_STM32_UART_40004C00_LABEL
#define CONFIG_UART_STM32_UART_4_BASE_ADDRESS ST_STM32_UART_40004C00_BASE_ADDRESS
#define CONFIG_UART_STM32_UART_4_BAUD_RATE ST_STM32_UART_40004C00_CURRENT_SPEED
#define CONFIG_UART_STM32_UART_4_IRQ_PRI ST_STM32_UART_40004C00_IRQ_0_PRIORITY
#define UART_4_IRQ ST_STM32_UART_40004C00_IRQ_0
#define CONFIG_UART_STM32_UART_5_NAME ST_STM32_UART_40005000_LABEL
#define CONFIG_UART_STM32_UART_5_BASE_ADDRESS ST_STM32_UART_40005000_BASE_ADDRESS
#define CONFIG_UART_STM32_UART_5_BAUD_RATE ST_STM32_UART_40005000_CURRENT_SPEED
#define CONFIG_UART_STM32_UART_5_IRQ_PRI ST_STM32_UART_40005000_IRQ_0_PRIORITY
#define UART_5_IRQ ST_STM32_UART_40005000_IRQ_0
/* End of SoC Level DTS fixup file */

4
arch/arm/soc/st_stm32/stm32f2/soc.h
View file

@ -36,6 +36,10 @@
#include <stm32f2xx_ll_system.h>
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
#ifdef CONFIG_SERIAL_HAS_DRIVER
#include <stm32f2xx_ll_usart.h>
#endif
#endif /* !_ASMLANGUAGE */
#endif /* _STM32F2_SOC_H_ */

3
drivers/serial/uart_stm32.c
View file

@ -99,7 +99,8 @@ static int uart_stm32_fifo_read(struct device *dev, u8_t *rx_data,
while ((size - num_rx > 0) &&
LL_USART_IsActiveFlag_RXNE(UartInstance)) {
#if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32F4X)
#if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32F4X) \
|| defined(CONFIG_SOC_SERIES_STM32F2X)
/* Clear the interrupt */
LL_USART_ClearFlag_RXNE(UartInstance);
#endif

38
dts/arm/st/stm32f2-pinctrl.dtsi
View file

@ -8,5 +8,43 @@
/ {
soc {
pinctrl: pin-controller@40020000 {
usart1_pins_a: usart1@0 {
rx_tx {
rx = <STM32_PIN_PB7 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PB6 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
usart1_pins_b: usart1@1 {
rx_tx {
rx = <STM32_PIN_PA10 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PA9 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
usart2_pins_a: usart2@0 {
rx_tx {
rx = <STM32_PIN_PA3 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PA2 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
usart2_pins_b: usart2@1 {
rx_tx {
rx = <STM32_PIN_PD5 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PD6 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
usart3_pins_a: usart3@0 {
rx_tx {
rx = <STM32_PIN_PB11 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PB10 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
usart3_pins_b: usart3@1 {
rx_tx {
rx = <STM32_PIN_PD9 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PD8 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
};
};
};

54
dts/arm/st/stm32f2.dtsi
View file

@ -137,6 +137,60 @@
label = "GPIOI";
};
};
usart1: serial@40011000 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
interrupts = <37 0>;
status = "disabled";
label = "UART_1";
};
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
interrupts = <38 0>;
status = "disabled";
label = "UART_2";
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
interrupts = <39 0>;
status = "disabled";
label = "UART_3";
};
usart6: serial@40011400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
interrupts = <71 0>;
status = "disabled";
label = "UART_6";
};
uart4: serial@40004c00 {
compatible ="st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
interrupts = <52 0>;
status = "disabled";
label = "UART_4";
};
uart5: serial@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
interrupts = <53 0>;
status = "disabled";
label = "UART_5";
};
};
};