From bc2a0b65a6a662f7555d9484381282658a24e1ba Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Fri, 4 Mar 2022 16:44:36 +0100 Subject: [PATCH] tests/drivers/clock_control: stm32u5: Fix pll_msis_80 test config PLL input should be between 4 and 16MHz, so when MSI is set to 4MHz fix PLLM can't be higher than 1. Fix PLL1-NQR in consequence. Signed-off-by: Erwan Gouriou --- ...ll_msis_ahb_2_80.overlay => pll_msis_ahb_2_40.overlay} | 8 ++++---- .../stm32_clock_configuration/stm32u5_core/testcase.yaml | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) rename tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/{pll_msis_ahb_2_80.overlay => pll_msis_ahb_2_40.overlay} (87%) diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_ahb_2_80.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_ahb_2_40.overlay similarity index 87% rename from tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_ahb_2_80.overlay rename to tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_ahb_2_40.overlay index d9c41e27f62..22748c9ee09 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_ahb_2_80.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_ahb_2_40.overlay @@ -21,9 +21,9 @@ &pll1 { div-m = <1>; - mul-n = <40>; - div-q = <1>; - div-r = <1>; + mul-n = <80>; + div-q = <4>; + div-r = <4>; clocks = <&clk_msis>; status = "okay"; }; @@ -31,7 +31,7 @@ &rcc { clocks = <&pll1>; ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */ - clock-frequency = ; + clock-frequency = ; apb1-prescaler = <1>; apb2-prescaler = <1>; apb3-prescaler = <1>; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml index 5298b3416da..be7a98cd596 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml @@ -4,8 +4,8 @@ common: tests: drivers.stm32_clock_configuration.u5.sysclksrc_pll_msis_160: extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_160.overlay" - drivers.stm32_clock_configuration.u5.pll_msis_hab_2_80: - extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_ahb_2_80.overlay" + drivers.stm32_clock_configuration.u5.pll_msis_hab_2_40: + extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_ahb_2_40.overlay" drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_160: extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_160.overlay" drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_40: