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tests: drivers: uart_async: stm32: add test cases with DCache enabled

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Add test cases/configs for async DMA uart with DCache on STM32F7/H7 boards

Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
This commit is contained in:
Abderrahmane Jarmouni 2024-03-20 15:39:18 +01:00 • committed by Anas Nashif
commit b903dff44f
5 changed files with 79 additions and 3 deletions
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17
tests/drivers/uart/uart_async_api/boards/nucleo_f746zg_nocachemem.overlay Normal file
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@ -0,0 +1,17 @@
/*
* Copyright (c) 2024 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
/ {
/* The async_api.nocache_mem_dt test case expects a non-cachable RAM region */
sram_nocache: memory@2004c000 {
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x2004c000 DT_SIZE_K(16)>;
zephyr,memory-region = "RAM_NOCACHE";
zephyr,memory-attr = <DT_MEM_ARM_MPU_RAM_NOCACHE>;
};
};

13
tests/drivers/uart/uart_async_api/boards/nucleo_h723zg.overlay
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@ -1,11 +1,18 @@
/*
* Copyright (c) 2024 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
dut: &usart2 {
dmas = <&dmamux1 2 44 STM32_DMA_PERIPH_TX>,
<&dmamux1 3 43 STM32_DMA_PERIPH_RX>;
/* Arduino Header pins: Tx:D9, Rx:D10 */
dut: &uart9 {
pinctrl-0 = <&uart9_tx_pd15 &uart9_rx_pd14>;
pinctrl-names = "default";
current-speed = <115200>;
dmas = <&dmamux1 2 117 STM32_DMA_PERIPH_TX>,
<&dmamux1 3 116 STM32_DMA_PERIPH_RX>;
dma-names = "tx", "rx";
status = "okay";
};
&dma1 {

12
tests/drivers/uart/uart_async_api/boards/nucleo_h723zg_nocachemem.overlay Normal file
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@ -0,0 +1,12 @@
/*
* Copyright (c) 2024 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
&sram1 {
zephyr,memory-attr = <DT_MEM_ARM_MPU_RAM_NOCACHE>;
zephyr,memory-region = "RAM_NOCACHE";
};

4
tests/drivers/uart/uart_async_api/stm32_nocache_mem_dt.conf Normal file
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@ -0,0 +1,4 @@
CONFIG_DCACHE=y
CONFIG_DT_DEFINED_NOCACHE=y
CONFIG_DT_DEFINED_NOCACHE_NAME="RAM_NOCACHE"
CONFIG_USERSPACE=n

36
tests/drivers/uart/uart_async_api/testcase.yaml
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@ -74,3 +74,39 @@ tests:
- CONFIG_UART_SAM0_ASYNC=y
- CONFIG_DMA=y
build_only: true
drivers.uart.async_api.nocache_mem:
# nocache memory region is defined by the linker
filter: CONFIG_SERIAL_SUPPORT_ASYNC and CONFIG_CPU_HAS_DCACHE
harness: ztest
harness_config:
fixture: gpio_loopback
depends_on: gpio
platform_allow:
- nucleo_f746zg
- nucleo_h723zg
extra_configs:
- CONFIG_DCACHE=y
- CONFIG_NOCACHE_MEMORY=y
- CONFIG_USERSPACE=n
drivers.uart.async_api.nocache_mem_dt.nucleo_f746zg:
# nocache memory region is defined in DT
harness: ztest
harness_config:
fixture: gpio_loopback
depends_on: gpio
platform_allow:
- nucleo_f746zg
extra_args:
- DTC_OVERLAY_FILE="boards/nucleo_f746zg.overlay;boards/nucleo_f746zg_nocachemem.overlay"
- EXTRA_CONF_FILE=stm32_nocache_mem_dt.conf
drivers.uart.async_api.nocache_mem_dt.nucleo_h723zg:
# nocache memory region is defined in DT
harness: ztest
harness_config:
fixture: gpio_loopback
depends_on: gpio
platform_allow:
- nucleo_h723zg
extra_args:
- DTC_OVERLAY_FILE="boards/nucleo_h723zg.overlay;boards/nucleo_h723zg_nocachemem.overlay"
- EXTRA_CONF_FILE=stm32_nocache_mem_dt.conf