tests: drivers: uart_async: stm32: add test cases with DCache enabled
Add test cases/configs for async DMA uart with DCache on STM32F7/H7 boards Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
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5 changed files with 79 additions and 3 deletions
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/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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/ {
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/* The async_api.nocache_mem_dt test case expects a non-cachable RAM region */
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sram_nocache: memory@2004c000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x2004c000 DT_SIZE_K(16)>;
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zephyr,memory-region = "RAM_NOCACHE";
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zephyr,memory-attr = <DT_MEM_ARM_MPU_RAM_NOCACHE>;
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};
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};
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@ -1,11 +1,18 @@
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/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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dut: &usart2 {
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dmas = <&dmamux1 2 44 STM32_DMA_PERIPH_TX>,
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<&dmamux1 3 43 STM32_DMA_PERIPH_RX>;
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/* Arduino Header pins: Tx:D9, Rx:D10 */
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dut: &uart9 {
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pinctrl-0 = <&uart9_tx_pd15 &uart9_rx_pd14>;
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pinctrl-names = "default";
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current-speed = <115200>;
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dmas = <&dmamux1 2 117 STM32_DMA_PERIPH_TX>,
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<&dmamux1 3 116 STM32_DMA_PERIPH_RX>;
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dma-names = "tx", "rx";
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status = "okay";
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};
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&dma1 {
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/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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&sram1 {
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zephyr,memory-attr = <DT_MEM_ARM_MPU_RAM_NOCACHE>;
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zephyr,memory-region = "RAM_NOCACHE";
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};
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CONFIG_DCACHE=y
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CONFIG_DT_DEFINED_NOCACHE=y
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CONFIG_DT_DEFINED_NOCACHE_NAME="RAM_NOCACHE"
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CONFIG_USERSPACE=n
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@ -74,3 +74,39 @@ tests:
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- CONFIG_UART_SAM0_ASYNC=y
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- CONFIG_DMA=y
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build_only: true
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drivers.uart.async_api.nocache_mem:
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# nocache memory region is defined by the linker
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filter: CONFIG_SERIAL_SUPPORT_ASYNC and CONFIG_CPU_HAS_DCACHE
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harness: ztest
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harness_config:
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fixture: gpio_loopback
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depends_on: gpio
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platform_allow:
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- nucleo_f746zg
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- nucleo_h723zg
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extra_configs:
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- CONFIG_DCACHE=y
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- CONFIG_NOCACHE_MEMORY=y
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- CONFIG_USERSPACE=n
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drivers.uart.async_api.nocache_mem_dt.nucleo_f746zg:
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# nocache memory region is defined in DT
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harness: ztest
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harness_config:
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fixture: gpio_loopback
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depends_on: gpio
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platform_allow:
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- nucleo_f746zg
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extra_args:
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- DTC_OVERLAY_FILE="boards/nucleo_f746zg.overlay;boards/nucleo_f746zg_nocachemem.overlay"
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- EXTRA_CONF_FILE=stm32_nocache_mem_dt.conf
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drivers.uart.async_api.nocache_mem_dt.nucleo_h723zg:
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# nocache memory region is defined in DT
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harness: ztest
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harness_config:
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fixture: gpio_loopback
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depends_on: gpio
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platform_allow:
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- nucleo_h723zg
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extra_args:
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- DTC_OVERLAY_FILE="boards/nucleo_h723zg.overlay;boards/nucleo_h723zg_nocachemem.overlay"
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- EXTRA_CONF_FILE=stm32_nocache_mem_dt.conf
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