soc: arm: st_stm32: Add STM32G4 SoC series

Add soc and dts files to support for most of the common peripherals
in the STM32G4 series. Add specific support for the STM32G431RB.

Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>

dts/arm/st/g4/stm32g4.dtsi

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <arm/armv7-m.dtsi>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	soc {
+
+	};
+
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};

dts/arm/st/g4/stm32g431.dtsi

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g4/stm32g4.dtsi>

dts/arm/st/g4/stm32g431Xb.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g431.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};

soc/arm/st_stm32/stm32g4/CMakeLists.txt

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(
+  soc.c
+  )

soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series

@@ -0,0 +1,15 @@
+# Kconfig - STMicroelectronics STM32G4 MCU line
+#
+# Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_STM32G4X
+
+source "soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g4*"
+
+config SOC_SERIES
+	default "stm32g4"
+
+endif # SOC_SERIES_STM32G4X

soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g431rb

@@ -0,0 +1,21 @@
+# Kconfig - STMicroelectronics STM32G431RB MCU
+#
+# Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32G431XX
+
+config SOC
+	string
+	default "stm32g431xx"
+
+config NUM_IRQS
+	int
+	default 102
+
+if GPIO_STM32
+
+endif # GPIO_STM32
+endif # SOC_STM32G431XX

soc/arm/st_stm32/stm32g4/Kconfig.series

@@ -0,0 +1,16 @@
+# Kconfig - STMicroelectronics STM32G4 MCU series
+#
+# Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_STM32G4X
+	bool "STM32G4x Series MCU"
+	select CPU_CORTEX_M4
+	select CPU_HAS_FPU
+	select SOC_FAMILY_STM32
+	select HAS_STM32CUBE
+	select CPU_HAS_ARM_MPU
+	help
+	  Enable support for STM32G4 MCU series

soc/arm/st_stm32/stm32g4/Kconfig.soc

@@ -0,0 +1,15 @@
+# Kconfig - STMicroelectronics STM32G4 MCU line
+#
+# Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+prompt "STM32G4x MCU Selection"
+depends on SOC_SERIES_STM32G4X
+
+config SOC_STM32G431XX
+	bool "STM32G431XX"
+
+endchoice

soc/arm/st_stm32/stm32g4/dts_fixup.h

@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* SoC level DTS fixup file */
+
+#define DT_NUM_IRQ_PRIO_BITS			DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+/* End of SoC Level DTS fixup file */

soc/arm/st_stm32/stm32g4/linker.ld

@@ -0,0 +1,9 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/cortex_m/scripts/linker.ld>

soc/arm/st_stm32/stm32g4/soc.c

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for STM32G4 processor
+ */
+
+#include <device.h>
+#include <init.h>
+#include <arch/cpu.h>
+#include <cortex_m/exc.h>
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int stm32g4_init(struct device *arg)
+{
+	u32_t key;
+
+	ARG_UNUSED(arg);
+
+	key = irq_lock();
+
+	/* Install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	/* Update CMSIS SystemCoreClock variable (HCLK) */
+	/* At reset, system core clock is set to 16 MHz from HSI */
+	SystemCoreClock = 16000000;
+
+	return 0;
+}
+
+SYS_INIT(stm32g4_init, PRE_KERNEL_1, 0);

soc/arm/st_stm32/stm32g4/soc.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the STM32G4 family processors.
+ *
+ * Based on reference manual:
+ *   STM32G4xx advanced ARM ® -based 32-bit MCUs
+ *
+ * Chapter 2.2: Memory organization
+ */
+
+
+#ifndef _STM32G4_SOC_H_
+#define _STM32G4_SOC_H_
+
+#include <sys/util.h>
+
+#ifndef _ASMLANGUAGE
+
+#include <autoconf.h>
+#include <stm32g4xx.h>
+
+/* Add include for DTS generated information */
+#include <generated_dts_board.h>
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32G4_SOC_H_ */