boards: mimxrt685_evk/mimxrt685s/cm33: Enable DMIC
Enable DMIC clock in soc.c - attach to chip's audio PLL. Add pinmux definitions for the DMIC peripheral. Add nodes to SoC's device tree for the DMIC peripheral and its audio channels. Configure the DMIC peripheral in board's device tree to enable audio capture. Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
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4 changed files with 114 additions and 1 deletions
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@ -82,6 +82,16 @@
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};
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};
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};
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};
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pinmux_dmic0: pinmux_dmic0 {
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group0 {
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pinmux = <DMIC0_DATA2_3_PIO2_21>, <DMIC0_DATA0_1_PIO2_20>,
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<DMIC0_CLK0_1_PIO2_16>;
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slew-rate = "normal";
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drive-strength = "normal";
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input-enable;
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};
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};
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pinmux_flexspi: pinmux_flexspi {
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pinmux_flexspi: pinmux_flexspi {
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group0 {
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group0 {
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pinmux = <FLEXSPI0B_DATA0_PIO1_11>,
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pinmux = <FLEXSPI0B_DATA0_PIO1_11>,
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2020-2023, NXP
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* Copyright 2020-2024 NXP
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@ -33,6 +33,7 @@
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magn0 = &fxos8700;
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magn0 = &fxos8700;
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accel0 = &fxos8700;
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accel0 = &fxos8700;
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sdhc0 = &usdhc0;
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sdhc0 = &usdhc0;
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dmic-dev = &dmic0;
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};
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};
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chosen {
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chosen {
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@ -396,3 +397,27 @@ zephyr_udc0: &usbhs {
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&sram1 {
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&sram1 {
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status = "okay";
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status = "okay";
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};
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};
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&dmic0 {
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status = "okay";
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pinctrl-0 = <&pinmux_dmic0>;
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pinctrl-names = "default";
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use2fs;
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};
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/* Configure pdm channels 0 and 1 with gain, and cutoff settings
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* appropriate for the attached MEMS microphones.
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*/
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&pdmc0 {
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status = "okay";
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gainshift = <3>;
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dc-cutoff = "155hz";
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dc-gain = <1>;
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};
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&pdmc1 {
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status = "okay";
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gainshift = <3>;
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dc-cutoff = "155hz";
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dc-gain = <1>;
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};
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@ -335,6 +335,72 @@
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#dma-cells = <1>;
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#dma-cells = <1>;
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};
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};
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dmic0: dmic@121000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,dmic";
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reg = <0x121000 0x1000>;
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interrupts = <25 0>;
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status = "disabled";
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clocks = <&clkctl0 MCUX_DMIC_CLK>;
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pdmc0: dmic-channel@0 {
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compatible = "nxp,dmic-channel";
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reg = <0>;
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dmas = <&dma0 16>;
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status = "disabled";
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};
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pdmc1: dmic-channel@1 {
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compatible = "nxp,dmic-channel";
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reg = <1>;
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dmas = <&dma0 17>;
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status = "disabled";
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};
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pdmc2: dmic-channel@2 {
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compatible = "nxp,dmic-channel";
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reg = <2>;
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dmas = <&dma0 18>;
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status = "disabled";
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};
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pdmc3: dmic-channel@3 {
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compatible = "nxp,dmic-channel";
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reg = <3>;
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dmas = <&dma0 19>;
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status = "disabled";
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};
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pdmc4: dmic-channel@4 {
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compatible = "nxp,dmic-channel";
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reg = <4>;
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dmas = <&dma0 20>;
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status = "disabled";
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};
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pdmc5: dmic-channel@5 {
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compatible = "nxp,dmic-channel";
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reg = <5>;
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dmas = <&dma0 21>;
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status = "disabled";
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};
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pdmc6: dmic-channel@6 {
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compatible = "nxp,dmic-channel";
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reg = <6>;
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dmas = <&dma0 22>;
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status = "disabled";
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};
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pdmc7: dmic-channel@7 {
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compatible = "nxp,dmic-channel";
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reg = <7>;
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dmas = <&dma0 23>;
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status = "disabled";
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};
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};
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os_timer: timers@113000 {
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os_timer: timers@113000 {
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compatible = "nxp,os-timer";
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compatible = "nxp,os-timer";
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reg = <0x113000 0x1000>;
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reg = <0x113000 0x1000>;
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@ -310,6 +310,18 @@ static ALWAYS_INLINE void clock_init(void)
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CLOCK_SetClkDiv(kCLOCK_DivAdcClk, DT_PROP(DT_NODELABEL(lpadc0), clk_divider));
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CLOCK_SetClkDiv(kCLOCK_DivAdcClk, DT_PROP(DT_NODELABEL(lpadc0), clk_divider));
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#endif
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(dmic0), nxp_dmic, okay)
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/* Using the Audio PLL as input clock leads to better clock dividers
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* for typical PCM sample rates ({8,16,24,32,48,96} kHz.
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*/
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/* DMIC source from audio pll, divider 8, 24.576M/8=3.072MHZ
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* Select Audio PLL as clock source. This should produce a bit clock
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* of 3.072MHZ
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*/
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CLOCK_AttachClk(kAUDIO_PLL_to_DMIC_CLK);
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CLOCK_SetClkDiv(kCLOCK_DivDmicClk, 8);
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#endif
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#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP
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#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP
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/*
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/*
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* Call function flexspi_setup_clock() to set user configured clock source/divider
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* Call function flexspi_setup_clock() to set user configured clock source/divider
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