diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk-pinctrl.dtsi b/boards/nxp/mimxrt685_evk/mimxrt685_evk-pinctrl.dtsi
index 63febf90fce..7a7b6b9c7bd 100644
--- a/boards/nxp/mimxrt685_evk/mimxrt685_evk-pinctrl.dtsi
+++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk-pinctrl.dtsi
@@ -82,6 +82,16 @@
 		};
 	};
 
+	pinmux_dmic0: pinmux_dmic0 {
+		group0 {
+			pinmux = <DMIC0_DATA2_3_PIO2_21>, <DMIC0_DATA0_1_PIO2_20>,
+			       <DMIC0_CLK0_1_PIO2_16>;
+			slew-rate = "normal";
+			drive-strength = "normal";
+			input-enable;
+		};
+	};
+
 	pinmux_flexspi: pinmux_flexspi {
 		group0 {
 			pinmux = <FLEXSPI0B_DATA0_PIO1_11>,
diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts
index 79ced2d7898..d4b59332467 100644
--- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts
+++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2023, NXP
+ * Copyright 2020-2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -33,6 +33,7 @@
 		magn0 = &fxos8700;
 		accel0 = &fxos8700;
 		sdhc0 = &usdhc0;
+		dmic-dev = &dmic0;
 	};
 
 	chosen {
@@ -396,3 +397,27 @@ zephyr_udc0: &usbhs {
 &sram1 {
 	status = "okay";
 };
+
+&dmic0 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_dmic0>;
+	pinctrl-names = "default";
+	use2fs;
+};
+
+/* Configure pdm channels 0 and 1 with gain, and cutoff settings
+ * appropriate for the attached MEMS microphones.
+ */
+&pdmc0 {
+	status = "okay";
+	gainshift = <3>;
+	dc-cutoff = "155hz";
+	dc-gain = <1>;
+};
+
+&pdmc1 {
+	status = "okay";
+	gainshift = <3>;
+	dc-cutoff = "155hz";
+	dc-gain = <1>;
+};
diff --git a/dts/arm/nxp/nxp_rt6xx_common.dtsi b/dts/arm/nxp/nxp_rt6xx_common.dtsi
index 510c0f45bb3..2b36664f757 100644
--- a/dts/arm/nxp/nxp_rt6xx_common.dtsi
+++ b/dts/arm/nxp/nxp_rt6xx_common.dtsi
@@ -335,6 +335,72 @@
 		#dma-cells = <1>;
 	};
 
+	dmic0: dmic@121000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nxp,dmic";
+		reg = <0x121000 0x1000>;
+		interrupts = <25 0>;
+		status = "disabled";
+		clocks = <&clkctl0 MCUX_DMIC_CLK>;
+
+		pdmc0: dmic-channel@0 {
+			compatible = "nxp,dmic-channel";
+			reg = <0>;
+			dmas = <&dma0 16>;
+			status = "disabled";
+		};
+
+		pdmc1: dmic-channel@1 {
+			compatible = "nxp,dmic-channel";
+			reg = <1>;
+			dmas = <&dma0 17>;
+			status = "disabled";
+		};
+
+		pdmc2: dmic-channel@2 {
+			compatible = "nxp,dmic-channel";
+			reg = <2>;
+			dmas = <&dma0 18>;
+			status = "disabled";
+		};
+
+		pdmc3: dmic-channel@3 {
+			compatible = "nxp,dmic-channel";
+			reg = <3>;
+			dmas = <&dma0 19>;
+			status = "disabled";
+		};
+
+		pdmc4: dmic-channel@4 {
+			compatible = "nxp,dmic-channel";
+			reg = <4>;
+			dmas = <&dma0 20>;
+			status = "disabled";
+		};
+
+		pdmc5: dmic-channel@5 {
+			compatible = "nxp,dmic-channel";
+			reg = <5>;
+			dmas = <&dma0 21>;
+			status = "disabled";
+		};
+
+		pdmc6: dmic-channel@6 {
+			compatible = "nxp,dmic-channel";
+			reg = <6>;
+			dmas = <&dma0 22>;
+			status = "disabled";
+		};
+
+		pdmc7: dmic-channel@7 {
+			compatible = "nxp,dmic-channel";
+			reg = <7>;
+			dmas = <&dma0 23>;
+			status = "disabled";
+		};
+	};
+
 	os_timer: timers@113000 {
 		compatible = "nxp,os-timer";
 		reg = <0x113000 0x1000>;
diff --git a/soc/nxp/imxrt/imxrt6xx/cm33/soc.c b/soc/nxp/imxrt/imxrt6xx/cm33/soc.c
index ffec56a099b..523ef4df351 100644
--- a/soc/nxp/imxrt/imxrt6xx/cm33/soc.c
+++ b/soc/nxp/imxrt/imxrt6xx/cm33/soc.c
@@ -310,6 +310,18 @@ static ALWAYS_INLINE void clock_init(void)
 	CLOCK_SetClkDiv(kCLOCK_DivAdcClk, DT_PROP(DT_NODELABEL(lpadc0), clk_divider));
 #endif
 
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(dmic0), nxp_dmic, okay)
+	/* Using the Audio PLL as input clock leads to better clock dividers
+	 * for typical PCM sample rates ({8,16,24,32,48,96} kHz.
+	 */
+	/* DMIC source from audio pll, divider 8, 24.576M/8=3.072MHZ
+	 * Select Audio PLL as clock source. This should produce a bit clock
+	 * of 3.072MHZ
+	 */
+	CLOCK_AttachClk(kAUDIO_PLL_to_DMIC_CLK);
+	CLOCK_SetClkDiv(kCLOCK_DivDmicClk, 8);
+#endif
+
 #ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP
 	/*
 	 * Call function flexspi_setup_clock() to set user configured clock source/divider