drivers: cavs_timer: Use the new interrupt controller API
Recent work to this platform added a new, cleaner low level API to the interrupt controller. Replace the hand-cooked register access with that. This is still not as good as having proper multicore support in the intc_cavs driver, but it's at least better. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
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1 changed files with 2 additions and 4 deletions
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@ -7,6 +7,7 @@
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#include <drivers/timer/system_timer.h>
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#include <sys_clock.h>
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#include <spinlock.h>
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#include <cavs-idc.h>
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/**
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* @file
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@ -195,9 +196,6 @@ void smp_timer_init(void)
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* FIXME: Done in this way because we don't have an API
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* to enable interrupts per CPU.
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*/
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sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs0))
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+ CAVS_ICTL_INT_CPU_OFFSET(arch_curr_cpu()->id)
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+ 0x04,
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22 + TIMER);
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CAVS_INTCTRL[arch_curr_cpu()->id].l2.clear = CAVS_L2_DWCT0;
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irq_enable(TIMER_IRQ);
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}
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