adc: QMSI ADC driver
This creates the QMSI ADC driver which is simply a shim driver based on the ADC driver provided by QMSI BSP. In order to enable this driver, the following options should be set: CONFIG_QMSI_DRIVERS=y CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory" CONFIG_ADC=y CONFIG_ADC_QMSI=y Optionally this can be set: CONFIG_ADC_IRQ CONFIG_ADC_PRI CONFIG_ADC_QMSI_POLL CONFIG_ADC_QMSI_INTERRUPT CONFIG_ADC_QMSI_CALIBRATION CONFIG_ADC_QMSI_CLOCK_RATIO CONFIG_ADC_QMSI_SERIAL_DELAY CONFIG_ADC_QMSI_SAMPLE_WIDTH Origin of the file: This file has been created from scratch Change-Id: Ie04776ac2ed88e56852409070edec568974f8e0d Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
This commit is contained in:
Sergio Rodriguez
Gerrit Code Review
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3 changed files with 360 additions and 0 deletions
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@ -209,3 +209,77 @@ config ADC_DW_CLOCK_RATIO
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ADC Clock Ratio
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endif
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config ADC_QMSI
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bool "QMSI ADC Driver"
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depends on QMSI_DRIVERS && ADC
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default n
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help
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Enable the driver implementation of the QMSI ADC IP.
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config ADC_QMSI_NAME
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string "Select a name to lookup the device"
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default "ADC"
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depends on ADC_QMSI
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config ADC_IRQ
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int
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prompt "ADC interrupt request"
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depends on ADC_QMSI
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default 9
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config ADC_PRI
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int
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prompt "ADC interrupt priority"
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depends on ADC_QMSI
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default 2
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choice
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prompt "Capturing Mode"
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default ADC_QMSI_INTERRUPT
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depends on ADC_QMSI
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help
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ADC sample capture mode - interrupt mode/polling mode
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config ADC_QMSI_POLL
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bool "Polling samples"
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config ADC_QMSI_INTERRUPT
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bool "Interrupt notification"
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endchoice
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config ADC_QMSI_CALIBRATION
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bool "Enable Calibration"
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default y
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depends on ADC_QMSI
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help
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Enables ADC to run with a calibrated output at the
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expense of execution speed when exiting low power states.
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If disabled, the ADC will require the application/system-integrator
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to provide a calibration method.
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config ADC_QMSI_CLOCK_RATIO
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int "Clock Ratio"
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default 100
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help
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ADC Clock Ratio
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config ADC_QMSI_SERIAL_DELAY
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int "Serial Delay"
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default 1
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help
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Number of ADC clock ticks that the first bit of
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the serial output is delayed after the conversion
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has started.
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config ADC_QMSI_SAMPLE_WIDTH
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int "Sample Width"
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depends on ADC_QMSI
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default 3
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help
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Defines ADC device data sample width (resolution):
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0 = 6 bits resolution
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1 = 8 bits resolution
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2 = 10 bits resolution
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3 = 12 bits resolution
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@ -1,2 +1,5 @@
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ccflags-$(CONFIG_ADC_QMSI) += -I$(CONFIG_QMSI_INSTALL_PATH)/include
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obj-$(CONFIG_ADC_DW) += adc_dw.o
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obj-$(CONFIG_ADC_TI_ADC108S102) += adc_ti_adc108s102.o
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obj-$(CONFIG_ADC_QMSI) += adc_qmsi.o
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283
drivers/adc/adc_qmsi.c
Normal file
283
drivers/adc/adc_qmsi.c
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@ -0,0 +1,283 @@
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/* adc_qmsi.c - QMSI ADC driver */
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/*
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* Copyright (c) 2016 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <init.h>
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#include <nanokernel.h>
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#include <string.h>
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#include <stdlib.h>
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#include <board.h>
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#include <adc.h>
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#include <arch/cpu.h>
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#include <atomic.h>
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#include "qm_adc.h"
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#include "qm_scss.h"
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enum {
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ADC_STATE_IDLE,
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ADC_STATE_BUSY,
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ADC_STATE_ERROR
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};
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struct adc_info {
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atomic_t state;
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device_sync_call_t sync;
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struct nano_sem sem;
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};
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static struct adc_info *adc_context;
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static void adc_config_irq(void);
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static void complete_callback(void)
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{
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if (adc_context) {
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device_sync_call_complete(&adc_context->sync);
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}
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}
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static void error_callback(void)
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{
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if (adc_context) {
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adc_context->state = ADC_STATE_ERROR;
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device_sync_call_complete(&adc_context->sync);
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}
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}
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static void adc_lock(struct adc_info *data)
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{
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nano_sem_take(&data->sem, TICKS_UNLIMITED);
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data->state = ADC_STATE_BUSY;
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}
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static void adc_unlock(struct adc_info *data)
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{
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nano_sem_give(&data->sem);
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data->state = ADC_STATE_IDLE;
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}
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#if (CONFIG_ADC_QMSI_CALIBRATION)
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static void adc_qmsi_enable(struct device *dev)
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{
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struct adc_info *info = dev->driver_data;
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adc_lock(info);
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qm_adc_set_mode(QM_ADC_0, QM_ADC_MODE_NORM_CAL);
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qm_adc_calibrate(QM_ADC_0);
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adc_unlock(info);
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}
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#else
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static void adc_qmsi_enable(struct device *dev)
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{
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struct adc_info *info = dev->driver_data;
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adc_lock(info);
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qm_adc_set_mode(QM_ADC_0, QM_ADC_MODE_NORM_NO_CAL);
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adc_unlock(info);
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}
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#endif /* CONFIG_ADC_QMSI_CALIBRATION */
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static void adc_qmsi_disable(struct device *dev)
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{
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struct adc_info *info = dev->driver_data;
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adc_lock(info);
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/* Go to deep sleep */
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qm_adc_set_mode(QM_ADC_0, QM_ADC_MODE_DEEP_PWR_DOWN);
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adc_unlock(info);
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}
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#if (CONFIG_ADC_QMSI_POLL)
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static int adc_qmsi_read(struct device *dev, struct adc_seq_table *seq_tbl)
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{
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int i, ret = DEV_OK;
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qm_adc_xfer_t xfer;
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qm_adc_config_t cfg;
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struct adc_info *info = dev->driver_data;
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if (qm_adc_get_config(QM_ADC_0, &cfg) != QM_RC_OK) {
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return DEV_INVALID_OP;
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}
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for (i = 0; i < seq_tbl->num_entries; i++) {
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xfer.ch = (qm_adc_channel_t *)&seq_tbl->entries[i].channel_id;
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/* Just one channel at the time using the Zephyr sequence table */
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xfer.ch_len = 1;
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xfer.samples = (uint32_t *)seq_tbl->entries[i].buffer;
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/* buffer length (bytes) the number of samples, the QMSI Driver does
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* not allow more than QM_ADC_FIFO_LEN samples at the time in polling
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* mode, if that happens, the qm_adc_convert api will return with an
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* error
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*/
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xfer.samples_len = (seq_tbl->entries[i].buffer_length);
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xfer.complete_callback = NULL;
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xfer.error_callback = NULL;
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cfg.window = seq_tbl->entries[i].sampling_delay;
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adc_lock(info);
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if (qm_adc_set_config(QM_ADC_0, &cfg) != QM_RC_OK) {
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ret = DEV_INVALID_CONF;
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adc_unlock(info);
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break;
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}
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/* Run the conversion, here the function will poll for the samples
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* The function will constantly read the status register to check if
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* the number of samples required has been captured
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*/
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if (qm_adc_convert(QM_ADC_0, &xfer) != QM_RC_OK) {
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ret = DEV_FAIL;
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adc_unlock(info);
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break;
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}
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/* Successful Analog to Digital conversion */
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adc_unlock(info);
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}
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return ret;
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}
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#else
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static int adc_qmsi_read(struct device *dev, struct adc_seq_table *seq_tbl)
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{
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int i, ret = DEV_OK;
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qm_adc_xfer_t xfer;
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qm_adc_config_t cfg;
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struct adc_info *info = dev->driver_data;
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if (qm_adc_get_config(QM_ADC_0, &cfg) != QM_RC_OK) {
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return DEV_INVALID_OP;
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}
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for (i = 0; i < seq_tbl->num_entries; i++) {
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xfer.ch = (qm_adc_channel_t *)&seq_tbl->entries[i].channel_id;
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/* Just one channel at the time using the Zephyr sequence table */
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xfer.ch_len = 1;
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xfer.samples = (uint32_t *)seq_tbl->entries[i].buffer;
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xfer.samples_len = (seq_tbl->entries[i].buffer_length) >> 2;
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xfer.complete_callback = complete_callback;
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xfer.error_callback = error_callback;
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cfg.window = seq_tbl->entries[i].sampling_delay;
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adc_lock(info);
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if (qm_adc_set_config(QM_ADC_0, &cfg) != QM_RC_OK) {
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ret = DEV_INVALID_CONF;
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adc_unlock(info);
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break;
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}
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/* ADC info used by the callbacks */
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adc_context = info;
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/* This is the interrupt driven API, will generate and interrupt and
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* call the complete_callback function once the samples have been
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* obtained
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*/
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if (qm_adc_irq_convert(QM_ADC_0, &xfer) != QM_RC_OK) {
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adc_context = NULL;
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ret = DEV_FAIL;
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adc_unlock(info);
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break;
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}
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/* Wait for the interrupt to finish */
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device_sync_call_wait(&info->sync);
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if (info->state == ADC_STATE_ERROR) {
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ret = DEV_FAIL;
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adc_unlock(info);
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break;
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}
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adc_context = NULL;
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/* Successful Analog to Digital conversion */
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adc_unlock(info);
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}
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return ret;
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}
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#endif /* CONFIG_ADC_QMSI_POLL */
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void adc_qmsi_isr(void *arg)
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{
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qm_adc_0_isr();
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}
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static struct adc_driver_api api_funcs = {
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.enable = adc_qmsi_enable,
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.disable = adc_qmsi_disable,
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.read = adc_qmsi_read,
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};
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int adc_qmsi_init(struct device *dev)
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{
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qm_adc_config_t cfg;
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struct adc_info *info = dev->driver_data;
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dev->driver_api = &api_funcs;
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/* Enable the ADC and set the clock divisor */
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clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_ADC |
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CLK_PERIPH_ADC_REGISTER);
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/* ADC clock divider*/
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clk_adc_set_div(CONFIG_ADC_QMSI_CLOCK_RATIO);
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/* Set up config */
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/* Clock cycles between the start of each sample */
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cfg.window = CONFIG_ADC_QMSI_SERIAL_DELAY;
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cfg.resolution = CONFIG_ADC_QMSI_SAMPLE_WIDTH;
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qm_adc_set_config(QM_ADC_0, &cfg);
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device_sync_call_init(&info->sync);
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nano_sem_init(&info->sem);
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nano_sem_give(&info->sem);
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info->state = ADC_STATE_IDLE;
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adc_config_irq();
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return DEV_OK;
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}
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struct adc_info adc_info_dev;
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DEVICE_INIT(adc_qmsi, CONFIG_ADC_QMSI_NAME, &adc_qmsi_init,
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&adc_info_dev, NULL,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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static void adc_config_irq(void)
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{
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IRQ_CONNECT(CONFIG_ADC_IRQ, CONFIG_ADC_PRI, qm_adc_0_isr,
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NULL, (IOAPIC_LEVEL | IOAPIC_HIGH));
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irq_enable(CONFIG_ADC_IRQ);
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QM_SCSS_INT->int_adc_calib_mask &= ~BIT(0);
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}
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