From b47df6e800e7820f3dc7dc14330c16c44f2506e4 Mon Sep 17 00:00:00 2001 From: Sergio Rodriguez Date: Thu, 25 Feb 2016 17:24:16 -0800 Subject: [PATCH] adc: QMSI ADC driver This creates the QMSI ADC driver which is simply a shim driver based on the ADC driver provided by QMSI BSP. In order to enable this driver, the following options should be set: CONFIG_QMSI_DRIVERS=y CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory" CONFIG_ADC=y CONFIG_ADC_QMSI=y Optionally this can be set: CONFIG_ADC_IRQ CONFIG_ADC_PRI CONFIG_ADC_QMSI_POLL CONFIG_ADC_QMSI_INTERRUPT CONFIG_ADC_QMSI_CALIBRATION CONFIG_ADC_QMSI_CLOCK_RATIO CONFIG_ADC_QMSI_SERIAL_DELAY CONFIG_ADC_QMSI_SAMPLE_WIDTH Origin of the file: This file has been created from scratch Change-Id: Ie04776ac2ed88e56852409070edec568974f8e0d Signed-off-by: Sergio Rodriguez --- drivers/adc/Kconfig | 74 +++++++++++ drivers/adc/Makefile | 3 + drivers/adc/adc_qmsi.c | 283 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 360 insertions(+) create mode 100644 drivers/adc/adc_qmsi.c diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index 0069f8a1943..be6166a67d4 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -209,3 +209,77 @@ config ADC_DW_CLOCK_RATIO ADC Clock Ratio endif + +config ADC_QMSI + bool "QMSI ADC Driver" + depends on QMSI_DRIVERS && ADC + default n + help + Enable the driver implementation of the QMSI ADC IP. + +config ADC_QMSI_NAME + string "Select a name to lookup the device" + default "ADC" + depends on ADC_QMSI + +config ADC_IRQ + int + prompt "ADC interrupt request" + depends on ADC_QMSI + default 9 + +config ADC_PRI + int + prompt "ADC interrupt priority" + depends on ADC_QMSI + default 2 + +choice + prompt "Capturing Mode" + default ADC_QMSI_INTERRUPT + depends on ADC_QMSI + help + ADC sample capture mode - interrupt mode/polling mode + +config ADC_QMSI_POLL + bool "Polling samples" + +config ADC_QMSI_INTERRUPT + bool "Interrupt notification" + +endchoice + +config ADC_QMSI_CALIBRATION + bool "Enable Calibration" + default y + depends on ADC_QMSI + help + Enables ADC to run with a calibrated output at the + expense of execution speed when exiting low power states. + If disabled, the ADC will require the application/system-integrator + to provide a calibration method. + +config ADC_QMSI_CLOCK_RATIO + int "Clock Ratio" + default 100 + help + ADC Clock Ratio + +config ADC_QMSI_SERIAL_DELAY + int "Serial Delay" + default 1 + help + Number of ADC clock ticks that the first bit of + the serial output is delayed after the conversion + has started. + +config ADC_QMSI_SAMPLE_WIDTH + int "Sample Width" + depends on ADC_QMSI + default 3 + help + Defines ADC device data sample width (resolution): + 0 = 6 bits resolution + 1 = 8 bits resolution + 2 = 10 bits resolution + 3 = 12 bits resolution \ No newline at end of file diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile index b5d75172532..7c8003f49a2 100644 --- a/drivers/adc/Makefile +++ b/drivers/adc/Makefile @@ -1,2 +1,5 @@ +ccflags-$(CONFIG_ADC_QMSI) += -I$(CONFIG_QMSI_INSTALL_PATH)/include + obj-$(CONFIG_ADC_DW) += adc_dw.o obj-$(CONFIG_ADC_TI_ADC108S102) += adc_ti_adc108s102.o +obj-$(CONFIG_ADC_QMSI) += adc_qmsi.o diff --git a/drivers/adc/adc_qmsi.c b/drivers/adc/adc_qmsi.c new file mode 100644 index 00000000000..b22c331e2e9 --- /dev/null +++ b/drivers/adc/adc_qmsi.c @@ -0,0 +1,283 @@ +/* adc_qmsi.c - QMSI ADC driver */ + +/* + * Copyright (c) 2016 Intel Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "qm_adc.h" +#include "qm_scss.h" + +enum { + ADC_STATE_IDLE, + ADC_STATE_BUSY, + ADC_STATE_ERROR +}; + +struct adc_info { + atomic_t state; + device_sync_call_t sync; + struct nano_sem sem; +}; + +static struct adc_info *adc_context; + +static void adc_config_irq(void); + +static void complete_callback(void) +{ + if (adc_context) { + device_sync_call_complete(&adc_context->sync); + } +} + +static void error_callback(void) +{ + if (adc_context) { + adc_context->state = ADC_STATE_ERROR; + device_sync_call_complete(&adc_context->sync); + } +} + +static void adc_lock(struct adc_info *data) +{ + nano_sem_take(&data->sem, TICKS_UNLIMITED); + data->state = ADC_STATE_BUSY; + +} +static void adc_unlock(struct adc_info *data) +{ + nano_sem_give(&data->sem); + data->state = ADC_STATE_IDLE; + +} +#if (CONFIG_ADC_QMSI_CALIBRATION) +static void adc_qmsi_enable(struct device *dev) +{ + struct adc_info *info = dev->driver_data; + + adc_lock(info); + qm_adc_set_mode(QM_ADC_0, QM_ADC_MODE_NORM_CAL); + qm_adc_calibrate(QM_ADC_0); + adc_unlock(info); +} + +#else +static void adc_qmsi_enable(struct device *dev) +{ + struct adc_info *info = dev->driver_data; + + adc_lock(info); + qm_adc_set_mode(QM_ADC_0, QM_ADC_MODE_NORM_NO_CAL); + adc_unlock(info); +} +#endif /* CONFIG_ADC_QMSI_CALIBRATION */ + +static void adc_qmsi_disable(struct device *dev) +{ + struct adc_info *info = dev->driver_data; + + adc_lock(info); + /* Go to deep sleep */ + qm_adc_set_mode(QM_ADC_0, QM_ADC_MODE_DEEP_PWR_DOWN); + adc_unlock(info); +} + +#if (CONFIG_ADC_QMSI_POLL) +static int adc_qmsi_read(struct device *dev, struct adc_seq_table *seq_tbl) +{ + int i, ret = DEV_OK; + qm_adc_xfer_t xfer; + qm_adc_config_t cfg; + + struct adc_info *info = dev->driver_data; + + if (qm_adc_get_config(QM_ADC_0, &cfg) != QM_RC_OK) { + return DEV_INVALID_OP; + } + + for (i = 0; i < seq_tbl->num_entries; i++) { + + xfer.ch = (qm_adc_channel_t *)&seq_tbl->entries[i].channel_id; + /* Just one channel at the time using the Zephyr sequence table */ + xfer.ch_len = 1; + xfer.samples = (uint32_t *)seq_tbl->entries[i].buffer; + + /* buffer length (bytes) the number of samples, the QMSI Driver does + * not allow more than QM_ADC_FIFO_LEN samples at the time in polling + * mode, if that happens, the qm_adc_convert api will return with an + * error + */ + xfer.samples_len = (seq_tbl->entries[i].buffer_length); + xfer.complete_callback = NULL; + xfer.error_callback = NULL; + + cfg.window = seq_tbl->entries[i].sampling_delay; + + adc_lock(info); + + if (qm_adc_set_config(QM_ADC_0, &cfg) != QM_RC_OK) { + ret = DEV_INVALID_CONF; + adc_unlock(info); + break; + } + + /* Run the conversion, here the function will poll for the samples + * The function will constantly read the status register to check if + * the number of samples required has been captured + */ + if (qm_adc_convert(QM_ADC_0, &xfer) != QM_RC_OK) { + ret = DEV_FAIL; + adc_unlock(info); + break; + } + + /* Successful Analog to Digital conversion */ + adc_unlock(info); + } + + return ret; +} +#else +static int adc_qmsi_read(struct device *dev, struct adc_seq_table *seq_tbl) +{ + int i, ret = DEV_OK; + qm_adc_xfer_t xfer; + qm_adc_config_t cfg; + + struct adc_info *info = dev->driver_data; + + if (qm_adc_get_config(QM_ADC_0, &cfg) != QM_RC_OK) { + return DEV_INVALID_OP; + } + + for (i = 0; i < seq_tbl->num_entries; i++) { + + xfer.ch = (qm_adc_channel_t *)&seq_tbl->entries[i].channel_id; + /* Just one channel at the time using the Zephyr sequence table */ + xfer.ch_len = 1; + xfer.samples = (uint32_t *)seq_tbl->entries[i].buffer; + xfer.samples_len = (seq_tbl->entries[i].buffer_length) >> 2; + xfer.complete_callback = complete_callback; + xfer.error_callback = error_callback; + + cfg.window = seq_tbl->entries[i].sampling_delay; + + adc_lock(info); + + if (qm_adc_set_config(QM_ADC_0, &cfg) != QM_RC_OK) { + ret = DEV_INVALID_CONF; + adc_unlock(info); + break; + } + + /* ADC info used by the callbacks */ + adc_context = info; + + /* This is the interrupt driven API, will generate and interrupt and + * call the complete_callback function once the samples have been + * obtained + */ + if (qm_adc_irq_convert(QM_ADC_0, &xfer) != QM_RC_OK) { + adc_context = NULL; + ret = DEV_FAIL; + adc_unlock(info); + break; + } + + /* Wait for the interrupt to finish */ + device_sync_call_wait(&info->sync); + + if (info->state == ADC_STATE_ERROR) { + ret = DEV_FAIL; + adc_unlock(info); + break; + } + adc_context = NULL; + + /* Successful Analog to Digital conversion */ + adc_unlock(info); + } + + return ret; +} +#endif /* CONFIG_ADC_QMSI_POLL */ + +void adc_qmsi_isr(void *arg) +{ + qm_adc_0_isr(); +} + +static struct adc_driver_api api_funcs = { + .enable = adc_qmsi_enable, + .disable = adc_qmsi_disable, + .read = adc_qmsi_read, +}; + +int adc_qmsi_init(struct device *dev) +{ + qm_adc_config_t cfg; + + struct adc_info *info = dev->driver_data; + + dev->driver_api = &api_funcs; + + /* Enable the ADC and set the clock divisor */ + clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_ADC | + CLK_PERIPH_ADC_REGISTER); + /* ADC clock divider*/ + clk_adc_set_div(CONFIG_ADC_QMSI_CLOCK_RATIO); + + /* Set up config */ + /* Clock cycles between the start of each sample */ + cfg.window = CONFIG_ADC_QMSI_SERIAL_DELAY; + cfg.resolution = CONFIG_ADC_QMSI_SAMPLE_WIDTH; + + qm_adc_set_config(QM_ADC_0, &cfg); + + device_sync_call_init(&info->sync); + + nano_sem_init(&info->sem); + nano_sem_give(&info->sem); + info->state = ADC_STATE_IDLE; + + adc_config_irq(); + + return DEV_OK; +} + +struct adc_info adc_info_dev; + +DEVICE_INIT(adc_qmsi, CONFIG_ADC_QMSI_NAME, &adc_qmsi_init, + &adc_info_dev, NULL, + SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); + +static void adc_config_irq(void) +{ + IRQ_CONNECT(CONFIG_ADC_IRQ, CONFIG_ADC_PRI, qm_adc_0_isr, + NULL, (IOAPIC_LEVEL | IOAPIC_HIGH)); + + irq_enable(CONFIG_ADC_IRQ); + + QM_SCSS_INT->int_adc_calib_mask &= ~BIT(0); +}